JPH0256446U - - Google Patents

Info

Publication number
JPH0256446U
JPH0256446U JP13479788U JP13479788U JPH0256446U JP H0256446 U JPH0256446 U JP H0256446U JP 13479788 U JP13479788 U JP 13479788U JP 13479788 U JP13479788 U JP 13479788U JP H0256446 U JPH0256446 U JP H0256446U
Authority
JP
Japan
Prior art keywords
package
hole
glass
external lead
insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13479788U
Other languages
Japanese (ja)
Other versions
JPH0723961Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1988134797U priority Critical patent/JPH0723961Y2/en
Publication of JPH0256446U publication Critical patent/JPH0256446U/ja
Application granted granted Critical
Publication of JPH0723961Y2 publication Critical patent/JPH0723961Y2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

Landscapes

  • Wire Bonding (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案の半導体素子収納用パツケージ
の一実施例を示す平面図、第２図は第１図に示す
パツケージの断面図、第３図は第１図に示すパツ
ケージに設けた位置認識用の穴の状態を説明する
ための部分拡大断面図、第４図は本考案の他の実
施例を示し、外部リード端子に設ける位置認識用
の穴の状態を説明するための部分拡大平面図であ
る。 １：絶縁基体、２：絶縁枠体、４：外部リード
端子、５：ガラス、８：穴。 Fig. 1 is a plan view showing an embodiment of the package for storing semiconductor elements of the present invention, Fig. 2 is a sectional view of the package shown in Fig. 1, and Fig. 3 is a position recognition device provided in the package shown in Fig. 1. FIG. 4 is a partially enlarged sectional view showing another embodiment of the present invention, and is a partially enlarged plan view showing the state of the position recognition hole provided in the external lead terminal. It is. 1: Insulating base, 2: Insulating frame, 4: External lead terminal, 5: Glass, 8: Hole.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 絶縁基板と絶縁枠体もしくは絶縁蓋体とを、そ
の間に多数の外部リード端子を挾んでガラス付け
して成る半導体素子収納用パツケージにおいて、
前記少なくとも１つの外部リード端子に位置認識
用の穴を形成するとともに該穴の下部にあるガラ
スを除去したことを特徴とする半導体素子収納用
パツケージ。 In a package for storing semiconductor elements, which is formed by attaching an insulating substrate and an insulating frame or an insulating cover with glass and sandwiching a large number of external lead terminals therebetween,
A package for housing a semiconductor device, characterized in that a hole for position recognition is formed in the at least one external lead terminal, and glass at the bottom of the hole is removed.
JP1988134797U 1988-10-14 1988-10-14 Package for storing semiconductor devices Expired - Fee Related JPH0723961Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1988134797U JPH0723961Y2 (en) 1988-10-14 1988-10-14 Package for storing semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1988134797U JPH0723961Y2 (en) 1988-10-14 1988-10-14 Package for storing semiconductor devices

Publications (2)

Publication Number Publication Date
JPH0256446U true JPH0256446U (en) 1990-04-24
JPH0723961Y2 JPH0723961Y2 (en) 1995-05-31

Family

ID=31393870

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1988134797U Expired - Fee Related JPH0723961Y2 (en) 1988-10-14 1988-10-14 Package for storing semiconductor devices

Country Status (1)

Country Link
JP (1) JPH0723961Y2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001024252A1 (en) * 1999-09-28 2001-04-05 Matsushita Electric Industrial Co., Ltd. Electronic device and method of manufacture thereof

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0224556U (en) * 1988-07-30 1990-02-19

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0224556U (en) * 1988-07-30 1990-02-19

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001024252A1 (en) * 1999-09-28 2001-04-05 Matsushita Electric Industrial Co., Ltd. Electronic device and method of manufacture thereof

Also Published As

Publication number Publication date
JPH0723961Y2 (en) 1995-05-31

Similar Documents

Publication Publication Date Title
JPH0256446U (en)
JPH0260242U (en)
JPH0254249U (en)
JPH02132951U (en)
JPH0363943U (en)
JPH0363944U (en)
JPH01154639U (en)
JPH0477260U (en)
JPH0165147U (en)
JPH0482849U (en)
JPH02142538U (en)
JPH02142541U (en)
JPH0482864U (en)
JPS62128674U (en)
JPS6349250U (en)
JPS62178671U (en)
JPS6333628U (en)
JPS636735U (en)
JPH02129739U (en)
JPS6221545U (en)
JPS6364047U (en)
JPS61151337U (en)
JPH0420236U (en)
JPS6249294U (en)
JPH0245651U (en)

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees