JPH0224556U - - Google Patents

Info

Publication number
JPH0224556U
JPH0224556U JP10122688U JP10122688U JPH0224556U JP H0224556 U JPH0224556 U JP H0224556U JP 10122688 U JP10122688 U JP 10122688U JP 10122688 U JP10122688 U JP 10122688U JP H0224556 U JPH0224556 U JP H0224556U
Authority
JP
Japan
Prior art keywords
lead
recognition
melting point
low melting
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10122688U
Other languages
Japanese (ja)
Other versions
JPH0713232Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP10122688U priority Critical patent/JPH0713232Y2/en
Publication of JPH0224556U publication Critical patent/JPH0224556U/ja
Application granted granted Critical
Publication of JPH0713232Y2 publication Critical patent/JPH0713232Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

Landscapes

  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の一実施例を示し、第１図ａは
キヤツプを取着する前の状態の平面図、第１図ｂ
はそのＡ−Ａ線断面図、第２図は本考案の他の実
施例の平面図、第３図ａ乃至第３図ｂは夫々認識
専用リードの先端部の異なる形状を示す部分平面
図、第４図は一般的なリード認識方法を説明する
ための模式的な図である。 １……セラミツク基板、２……低融点ガラス、
３……リードフレーム、３ａ……認識用リード、
３ｂ……認識専用リード、４……半導体素子、５
……金属細線、１１……認識装置、１２……２値
化画面、１３……光源。 Fig. 1 shows an embodiment of the present invention, Fig. 1a is a plan view of the state before the cap is attached, Fig. 1b
2 is a plan view of another embodiment of the present invention, and FIGS. 3a to 3b are partial plan views showing different shapes of the tip of the recognition lead, respectively. FIG. 4 is a schematic diagram for explaining a general lead recognition method. 1... Ceramic substrate, 2... Low melting point glass,
3...Lead frame, 3a...Recognition lead,
3b...Recognition-only lead, 4...Semiconductor element, 5
...Thin metal wire, 11...Recognition device, 12...Binarization screen, 13...Light source.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 基板上に低融点ガラスでリードフレームを固着
してなる半導体装置において、前記リードフレー
ムの一部をリード認識用のリードとして構成する
とともに、この認識用リードの下側及びその近傍
には前記低融点ガラスを配設しないように構成し
たことを特徴とするサーデイツプ型半導体装置。 In a semiconductor device in which a lead frame is fixed on a substrate with low melting point glass, a part of the lead frame is configured as a lead for lead recognition, and the low melting point glass is provided below and in the vicinity of this recognition lead. A semiconductor device of a dipping type characterized in that it is configured so that no glass is provided.
JP10122688U 1988-07-30 1988-07-30 Sardip type semiconductor device Expired - Lifetime JPH0713232Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10122688U JPH0713232Y2 (en) 1988-07-30 1988-07-30 Sardip type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10122688U JPH0713232Y2 (en) 1988-07-30 1988-07-30 Sardip type semiconductor device

Publications (2)

Publication Number Publication Date
JPH0224556U true JPH0224556U (en) 1990-02-19
JPH0713232Y2 JPH0713232Y2 (en) 1995-03-29

Family

ID=31330028

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10122688U Expired - Lifetime JPH0713232Y2 (en) 1988-07-30 1988-07-30 Sardip type semiconductor device

Country Status (1)

Country Link
JP (1) JPH0713232Y2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0256446U (en) * 1988-10-14 1990-04-24
JPH04111755U (en) * 1991-03-15 1992-09-29 ソニー株式会社 Inner lead shape of dip-type solid-state image sensor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0256446U (en) * 1988-10-14 1990-04-24
JPH04111755U (en) * 1991-03-15 1992-09-29 ソニー株式会社 Inner lead shape of dip-type solid-state image sensor

Also Published As

Publication number Publication date
JPH0713232Y2 (en) 1995-03-29

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