JPS58120665U - lead frame - Google Patents
lead frameInfo
- Publication number
- JPS58120665U JPS58120665U JP1674482U JP1674482U JPS58120665U JP S58120665 U JPS58120665 U JP S58120665U JP 1674482 U JP1674482 U JP 1674482U JP 1674482 U JP1674482 U JP 1674482U JP S58120665 U JPS58120665 U JP S58120665U
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- lead
- tip
- shape
- ceramic package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は従来のガラス封止型セラミックパッケージのリ
ードフレームの外形図、第2図は従来のリードフレーム
のリード端子の平面図である。第3図は本考案の実施例
のリードフレームのリード端子の先端に一例として切り
かきを入れた形状図、第4図はリード側にパターン認識
点をあてた図、′第5図は本考案のリードフレームと集
積回路素子部をワイヤボンディングした図である。
図中、1・・・・・・リードフレームの外形部、2・・
曲リード端子の先端部の形状、3・・・・・・集積回路
素子、4・・・・・・リード先端形状の一例、5・・間
パターン認識部、6・・・・・・ボンディングワイヤ、
である。FIG. 1 is an outline view of a lead frame of a conventional glass-sealed ceramic package, and FIG. 2 is a plan view of a lead terminal of the conventional lead frame. Figure 3 is a diagram showing the shape of the lead frame in accordance with the embodiment of the present invention, with a notch made as an example at the tip of the lead terminal, Figure 4 is a diagram showing pattern recognition points on the lead side, and Figure 5 is the shape of the lead frame according to the present invention. FIG. 3 is a diagram showing wire bonding between the lead frame and the integrated circuit element section. In the figure, 1...outline of the lead frame, 2...
Shape of tip of curved lead terminal, 3...Integrated circuit element, 4...Example of lead tip shape, 5...Interval pattern recognition section, 6...Bonding wire ,
It is.
Claims (1)
リードフレームの先端に切りかきパターンを設けること
を特徴とするリードフレーム。A lead frame used in a glass-sealed ceramic package type, characterized by having a cut pattern at the tip of the lead frame.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1674482U JPS58120665U (en) | 1982-02-09 | 1982-02-09 | lead frame |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1674482U JPS58120665U (en) | 1982-02-09 | 1982-02-09 | lead frame |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS58120665U true JPS58120665U (en) | 1983-08-17 |
Family
ID=30029102
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1674482U Pending JPS58120665U (en) | 1982-02-09 | 1982-02-09 | lead frame |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58120665U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04111755U (en) * | 1991-03-15 | 1992-09-29 | ソニー株式会社 | Inner lead shape of dip-type solid-state image sensor |
-
1982
- 1982-02-09 JP JP1674482U patent/JPS58120665U/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04111755U (en) * | 1991-03-15 | 1992-09-29 | ソニー株式会社 | Inner lead shape of dip-type solid-state image sensor |
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