JPS58144853U - hybrid IC - Google Patents

hybrid IC

Info

Publication number
JPS58144853U
JPS58144853U JP4168482U JP4168482U JPS58144853U JP S58144853 U JPS58144853 U JP S58144853U JP 4168482 U JP4168482 U JP 4168482U JP 4168482 U JP4168482 U JP 4168482U JP S58144853 U JPS58144853 U JP S58144853U
Authority
JP
Japan
Prior art keywords
hybrid
board
solder
mounting
pedestal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4168482U
Other languages
Japanese (ja)
Inventor
三郎 梅田
Original Assignee
株式会社日立製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社日立製作所 filed Critical 株式会社日立製作所
Priority to JP4168482U priority Critical patent/JPS58144853U/en
Publication of JPS58144853U publication Critical patent/JPS58144853U/en
Pending legal-status Critical Current

Links

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来技術による実装時の側面図、第２図は本考
案によるペデスタル形状と実装時の一実施例を示す正面
図と側面図、第３図は同じく他の実施例を示すペデスタ
ル形状の正面図である。 １．１１・・・セラミック基板、２．１２・・・ペデス
タル、３，１３・・・電極、４・・・実装部品、５．１
５・・・リード、１６．１７・・・切欠き。Fig. 1 is a side view when mounted according to the prior art, Fig. 2 is a front view and side view showing the pedestal shape according to the present invention and one embodiment when mounted, and Fig. 3 is a pedestal shape showing another embodiment. FIG. 1.11... Ceramic board, 2.12... Pedestal, 3, 13... Electrode, 4... Mounted component, 5.1
5...Lead, 16.17...Notch.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] デュアルインパッケージの半田溶融実装において、実装
基板のペデスタルの一部を矩形に切欠き、該基板を半田
ディツプしたとき凹状部を形成させて実装することを特
徴とする混成ＩＣ０In solder melt mounting of a dual-in package, a hybrid IC0 is characterized in that a part of the pedestal of a mounting board is cut out into a rectangular shape, and when the board is dipped in solder, a concave part is formed and mounted.
JP4168482U 1982-03-26 1982-03-26 hybrid IC Pending JPS58144853U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4168482U JPS58144853U (en) 1982-03-26 1982-03-26 hybrid IC

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4168482U JPS58144853U (en) 1982-03-26 1982-03-26 hybrid IC

Publications (1)

Publication Number Publication Date
JPS58144853U true JPS58144853U (en) 1983-09-29

Family

ID=30052860

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4168482U Pending JPS58144853U (en) 1982-03-26 1982-03-26 hybrid IC

Country Status (1)

Country Link
JP (1) JPS58144853U (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5180964A (en) * 1975-01-08 1976-07-15 Hitachi Ltd RIIDOKOTAI
JPS554962A (en) * 1978-06-27 1980-01-14 Hitachi Metals Ltd Microwave element
JPS554963A (en) * 1978-06-27 1980-01-14 Hitachi Metals Ltd Microwave element
JPS56142659A (en) * 1980-04-07 1981-11-07 Nec Corp Semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5180964A (en) * 1975-01-08 1976-07-15 Hitachi Ltd RIIDOKOTAI
JPS554962A (en) * 1978-06-27 1980-01-14 Hitachi Metals Ltd Microwave element
JPS554963A (en) * 1978-06-27 1980-01-14 Hitachi Metals Ltd Microwave element
JPS56142659A (en) * 1980-04-07 1981-11-07 Nec Corp Semiconductor device

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