JPS6333628U - - Google Patents

Info

Publication number
JPS6333628U
JPS6333628U JP12806286U JP12806286U JPS6333628U JP S6333628 U JPS6333628 U JP S6333628U JP 12806286 U JP12806286 U JP 12806286U JP 12806286 U JP12806286 U JP 12806286U JP S6333628 U JPS6333628 U JP S6333628U
Authority
JP
Japan
Prior art keywords
insulating base
semiconductor device
package
lid
recess
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12806286U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP12806286U priority Critical patent/JPS6333628U/ja
Publication of JPS6333628U publication Critical patent/JPS6333628U/ja
Pending legal-status Critical Current

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  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の半導体素子収納用パツケージ
の絶縁基体の一実施例を示す平面図、第2図は第
1図の絶縁基体を用いた半導体素子収納用パツケ
ージの断面図、第3図は従来の半導体素子収納用
パツケージの絶縁基体の平面図、第4図は第3図
の絶縁基体を用いた半導体素子収納用パツケージ
の断面図である。 1:絶縁基体、2:蓋体、3:絶縁容器、7:
外部リード端子、1a、1b、1c:位置合わせ
用凹部。
FIG. 1 is a plan view showing an embodiment of the insulating base of the semiconductor device housing package of the present invention, FIG. 2 is a cross-sectional view of the semiconductor device housing package using the insulating base of FIG. 1, and FIG. FIG. 4 is a plan view of an insulating base of a conventional semiconductor element housing package, and FIG. 4 is a sectional view of a semiconductor element housing package using the insulating base of FIG. 3. 1: Insulating base, 2: Lid, 3: Insulating container, 7:
External lead terminals, 1a, 1b, 1c: recesses for positioning.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 絶縁基体と蓋体とから成り、内部に半導体素子
を収納するための空所を有する半導体素子収納用
パツケージにおいて、前記絶縁基体の相対向する
側面のうち一方の側面に少なくとも1個の位置合
わせ用凹部を、他方の側面に少なくとも2個の位
置合わせ用凹部を設けたことを特徴とする半導体
素子収納用パツケージ。
In a semiconductor device storage package consisting of an insulating base and a lid and having a cavity for storing a semiconductor device inside, at least one positioning plate is provided on one of the opposing sides of the insulating base. 1. A package for housing a semiconductor element, comprising a recess and at least two positioning recesses provided on the other side.
JP12806286U 1986-08-21 1986-08-21 Pending JPS6333628U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12806286U JPS6333628U (en) 1986-08-21 1986-08-21

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12806286U JPS6333628U (en) 1986-08-21 1986-08-21

Publications (1)

Publication Number Publication Date
JPS6333628U true JPS6333628U (en) 1988-03-04

Family

ID=31023392

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12806286U Pending JPS6333628U (en) 1986-08-21 1986-08-21

Country Status (1)

Country Link
JP (1) JPS6333628U (en)

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