JPH0375535U - - Google Patents

Info

Publication number
JPH0375535U
JPH0375535U JP13776689U JP13776689U JPH0375535U JP H0375535 U JPH0375535 U JP H0375535U JP 13776689 U JP13776689 U JP 13776689U JP 13776689 U JP13776689 U JP 13776689U JP H0375535 U JPH0375535 U JP H0375535U
Authority
JP
Japan
Prior art keywords
lid
insulating base
semiconductor device
package
accommodating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13776689U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP13776689U priority Critical patent/JPH0375535U/ja
Publication of JPH0375535U publication Critical patent/JPH0375535U/ja
Pending legal-status Critical Current

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  • Packaging Frangible Articles (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の半導体素子収納用パツケージ
の一実施例を示す分解斜視図、第2図は第1図の
パツケージ内部に半導体素子を収容した状態を示
す断面図である。 1……絶縁基体、2……蓋体、3……絶縁容器
、6……外部リード端子、A……標識。
FIG. 1 is an exploded perspective view showing an embodiment of a package for housing semiconductor elements of the present invention, and FIG. 2 is a sectional view showing a state in which semiconductor elements are housed inside the package of FIG. 1. 1... Insulating base, 2... Lid, 3... Insulating container, 6... External lead terminal, A... Label.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 絶縁基体と蓋体とから成り、内部に半導体素子
を収容するための空所を有する半導体素子収納用
パツケージにおいて、前記絶縁基体もしくは蓋体
の外表面に底部の平坦度が50μm以下の凹状標
識を設けたことを特徴とする半導体素子収納用パ
ツケージ。
In a semiconductor device storage package consisting of an insulating base and a lid and having a cavity for accommodating a semiconductor device inside, a recessed mark with a bottom flatness of 50 μm or less is provided on the outer surface of the insulating base or the lid. A package cage for storing semiconductor elements, characterized by the following:
JP13776689U 1989-11-27 1989-11-27 Pending JPH0375535U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13776689U JPH0375535U (en) 1989-11-27 1989-11-27

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13776689U JPH0375535U (en) 1989-11-27 1989-11-27

Publications (1)

Publication Number Publication Date
JPH0375535U true JPH0375535U (en) 1991-07-29

Family

ID=31684909

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13776689U Pending JPH0375535U (en) 1989-11-27 1989-11-27

Country Status (1)

Country Link
JP (1) JPH0375535U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63175448A (en) * 1987-01-16 1988-07-19 Hitachi Ltd Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63175448A (en) * 1987-01-16 1988-07-19 Hitachi Ltd Semiconductor device

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