JPS636735U - - Google Patents
Info
- Publication number
- JPS636735U JPS636735U JP10109386U JP10109386U JPS636735U JP S636735 U JPS636735 U JP S636735U JP 10109386 U JP10109386 U JP 10109386U JP 10109386 U JP10109386 U JP 10109386U JP S636735 U JPS636735 U JP S636735U
- Authority
- JP
- Japan
- Prior art keywords
- relay terminal
- wiring pattern
- auxiliary relay
- terminal board
- side wall
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims 1
- 239000012212 insulator Substances 0.000 claims 1
- 238000001465 metallisation Methods 0.000 claims 1
- 229910052709 silver Inorganic materials 0.000 claims 1
- 239000004332 silver Substances 0.000 claims 1
- 238000007796 conventional method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Wire Bonding (AREA)
Description
第１図は本考案による一実施例を示す半導体装
置の斜視図、第２図は本考案による一実施例を示
す半導体装置の平面図、第３図は本考案の補助中
継端子板の構造を示す図、第４図は変更仕様に対
する従来技術を示す半導体装置の平面図、第５図
は設計仕様による半導体装置の平面図、である。
図において、１はケース、２は半導体素子、３
はリード、３ａは内部リード、３ｂは外部リード
、４は補助中継端子、４ａは絶縁基板、４ｂは配
線パターン、４ｃはボンデイングランド、５は素
子取付台、である。
FIG. 1 is a perspective view of a semiconductor device showing an embodiment of the invention, FIG. 2 is a plan view of a semiconductor device showing an embodiment of the invention, and FIG. 3 shows the structure of an auxiliary relay terminal board of the invention. FIG. 4 is a plan view of a semiconductor device showing a conventional technique for modified specifications, and FIG. 5 is a plan view of a semiconductor device according to design specifications. In the figure, 1 is a case, 2 is a semiconductor element, and 3 is a case.
3a is a lead, 3a is an internal lead, 3b is an external lead, 4 is an auxiliary relay terminal, 4a is an insulating substrate, 4b is a wiring pattern, 4c is a bonding ground, and 5 is an element mounting base.
Claims (1)
器１の該側壁の内側に補助中継端子板４を設け、
該補助中継端子板４は絶縁基板４ａ上に配線パタ
ーン４ｂをメタライズ加工により形成し、ボンデ
イングランド４ｃを該配線パターン４ｂ上に銀ろ
う付けしたことを特徴とする半導体装置。 An auxiliary relay terminal board 4 is provided inside the side wall of the storage container 1 in which the lead 3 is provided on the side wall via an insulator,
The auxiliary relay terminal board 4 is a semiconductor device characterized in that a wiring pattern 4b is formed on an insulating substrate 4a by metallization processing, and a bonding land 4c is silver soldered onto the wiring pattern 4b.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10109386U JPH0436110Y2 (en) | 1986-06-30 | 1986-06-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10109386U JPH0436110Y2 (en) | 1986-06-30 | 1986-06-30 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS636735U true JPS636735U (en) | 1988-01-18 |
| JPH0436110Y2 JPH0436110Y2 (en) | 1992-08-26 |
Family
ID=30971522
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10109386U Expired JPH0436110Y2 (en) | 1986-06-30 | 1986-06-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0436110Y2 (en) |
-
1986
- 1986-06-30 JP JP10109386U patent/JPH0436110Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0436110Y2 (en) | 1992-08-26 |