JPS63157954U - - Google Patents

Info

Publication number
JPS63157954U
JPS63157954U JP5069887U JP5069887U JPS63157954U JP S63157954 U JPS63157954 U JP S63157954U JP 5069887 U JP5069887 U JP 5069887U JP 5069887 U JP5069887 U JP 5069887U JP S63157954 U JPS63157954 U JP S63157954U
Authority
JP
Japan
Prior art keywords
view
space
electrode
lead
soldered
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5069887U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP5069887U priority Critical patent/JPS63157954U/ja
Publication of JPS63157954U publication Critical patent/JPS63157954U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は表面張力を説明する斜視図、第2図は
本考案による実装状態を示す一実施例の正面図、
第3図は第2図の側面図、第4図は本考案による
実装状態を示す他の実施例の側面図、第5図は従
来技術による実装状態を示す正面図、第6図は第
5図の側面図、第7図は従来技術による他の側面
図である。 図において、1はIC、1aはパツケージ、1
bはリード、1b―1は空間部、2はチツプコン
デンサ、2aはパツケージ、2bは電極、2b―
1は空間部、3,4はプリント基板、3a,4a
はランド、5は半田フイレツトを示す。
FIG. 1 is a perspective view illustrating surface tension, FIG. 2 is a front view of an embodiment of the present invention showing a state in which it is mounted.
3 is a side view of FIG. 2, FIG. 4 is a side view of another embodiment showing the mounting state according to the present invention, FIG. 5 is a front view showing the mounting state according to the prior art, and FIG. FIG. 7 is another side view according to the prior art. In the figure, 1 is an IC, 1a is a package, 1
b is a lead, 1b-1 is a space, 2 is a chip capacitor, 2a is a package, 2b is an electrode, 2b-
1 is a space, 3 and 4 are printed circuit boards, 3a and 4a
5 indicates a land, and 5 indicates a solder fillet.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 半田付けされるリード1bまたは電極2bを半
田接合面との間に空間部1b―1または2b―1
を有するように形成したことを特徴とする表面実
装部品。
A space 1b-1 or 2b-1 is provided between the lead 1b or electrode 2b to be soldered and the solder joint surface.
A surface mount component characterized in that it is formed to have.
JP5069887U 1987-04-02 1987-04-02 Pending JPS63157954U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5069887U JPS63157954U (en) 1987-04-02 1987-04-02

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5069887U JPS63157954U (en) 1987-04-02 1987-04-02

Publications (1)

Publication Number Publication Date
JPS63157954U true JPS63157954U (en) 1988-10-17

Family

ID=30874295

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5069887U Pending JPS63157954U (en) 1987-04-02 1987-04-02

Country Status (1)

Country Link
JP (1) JPS63157954U (en)

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