JPS6312380B2 - - Google Patents

Info

Publication number
JPS6312380B2
JPS6312380B2 JP57101101A JP10110182A JPS6312380B2 JP S6312380 B2 JPS6312380 B2 JP S6312380B2 JP 57101101 A JP57101101 A JP 57101101A JP 10110182 A JP10110182 A JP 10110182A JP S6312380 B2 JPS6312380 B2 JP S6312380B2
Authority
JP
Japan
Prior art keywords
silicon substrate
impurity
nitride film
region
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57101101A
Other languages
English (en)
Japanese (ja)
Other versions
JPS58216437A (ja
Inventor
Makoto Hirayama
Natsuo Tsubochi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP10110182A priority Critical patent/JPS58216437A/ja
Publication of JPS58216437A publication Critical patent/JPS58216437A/ja
Publication of JPS6312380B2 publication Critical patent/JPS6312380B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)
JP10110182A 1982-06-10 1982-06-10 半導体装置の製造方法 Granted JPS58216437A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10110182A JPS58216437A (ja) 1982-06-10 1982-06-10 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10110182A JPS58216437A (ja) 1982-06-10 1982-06-10 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JPS58216437A JPS58216437A (ja) 1983-12-16
JPS6312380B2 true JPS6312380B2 (enrdf_load_stackoverflow) 1988-03-18

Family

ID=14291692

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10110182A Granted JPS58216437A (ja) 1982-06-10 1982-06-10 半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JPS58216437A (enrdf_load_stackoverflow)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4637553B2 (ja) * 2004-11-22 2011-02-23 パナソニック株式会社 ショットキーバリアダイオード及びそれを用いた集積回路

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5429573A (en) * 1977-08-10 1979-03-05 Hitachi Ltd Fine machining method of semiconductor

Also Published As

Publication number Publication date
JPS58216437A (ja) 1983-12-16

Similar Documents

Publication Publication Date Title
JPH0513566A (ja) 半導体装置の製造方法
US4295266A (en) Method of manufacturing bulk CMOS integrated circuits
JP2521611B2 (ja) ツインウェルを有するcmosの製造方法
JPS63193562A (ja) バイポ−ラトランジスタの製造方法
US5369052A (en) Method of forming dual field oxide isolation
JPH02277253A (ja) 半導体装置の製造方法
JPS60106142A (ja) 半導体素子の製造方法
JPS6312380B2 (enrdf_load_stackoverflow)
JPH0268930A (ja) 半導体装置の製造法
JPH10308448A (ja) 半導体デバイスの隔離膜及びその形成方法
JP2820465B2 (ja) 半導体装置の製造方法
JPS61135136A (ja) 半導体装置の製造方法
JPS6237543B2 (enrdf_load_stackoverflow)
JPS6037614B2 (ja) 半導体装置の製造方法
JPS6025247A (ja) 半導体装置の製造方法
JP2775782B2 (ja) 半導体装置の製造方法
KR0135068B1 (ko) 반도체 소자간의 다중 활성영역 형성방법
JPH0680726B2 (ja) 半導体装置の製造方法
JPS6238857B2 (enrdf_load_stackoverflow)
JPH11340326A (ja) 半導体装置の製造方法
JPS63144543A (ja) 半導体素子間分離領域の形成方法
JPS6236390B2 (enrdf_load_stackoverflow)
JPS59942A (ja) 半導体装置の製造方法
JPS58149A (ja) 半導体装置
JPH0456457B2 (enrdf_load_stackoverflow)