JPS6255722B2 - - Google Patents

Info

Publication number
JPS6255722B2
JPS6255722B2 JP56191173A JP19117381A JPS6255722B2 JP S6255722 B2 JPS6255722 B2 JP S6255722B2 JP 56191173 A JP56191173 A JP 56191173A JP 19117381 A JP19117381 A JP 19117381A JP S6255722 B2 JPS6255722 B2 JP S6255722B2
Authority
JP
Japan
Prior art keywords
conductive layer
fet
package
gaas
gate electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56191173A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5892243A (ja
Inventor
Michio Irie
Shigeo Iki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP56191173A priority Critical patent/JPS5892243A/ja
Publication of JPS5892243A publication Critical patent/JPS5892243A/ja
Publication of JPS6255722B2 publication Critical patent/JPS6255722B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/501—Inductive arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
    • H10W72/07551—Controlling the environment, e.g. atmosphere composition or temperature characterised by changes in properties of the bond wires during the connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Junction Field-Effect Transistors (AREA)
  • Microwave Amplifiers (AREA)
JP56191173A 1981-11-27 1981-11-27 電界効果トランジスタ用パツケ−ジ Granted JPS5892243A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56191173A JPS5892243A (ja) 1981-11-27 1981-11-27 電界効果トランジスタ用パツケ−ジ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56191173A JPS5892243A (ja) 1981-11-27 1981-11-27 電界効果トランジスタ用パツケ−ジ

Publications (2)

Publication Number Publication Date
JPS5892243A JPS5892243A (ja) 1983-06-01
JPS6255722B2 true JPS6255722B2 (enExample) 1987-11-20

Family

ID=16270108

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56191173A Granted JPS5892243A (ja) 1981-11-27 1981-11-27 電界効果トランジスタ用パツケ−ジ

Country Status (1)

Country Link
JP (1) JPS5892243A (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60236508A (ja) * 1984-05-10 1985-11-25 Dx Antenna Co Ltd 広帯域増幅器
JPH02143604A (ja) * 1988-11-25 1990-06-01 Nec Corp 超高周波増幅器
JPH03263363A (ja) * 1990-02-23 1991-11-22 Fuji Electric Co Ltd 半導体装置
JP2008056389A (ja) * 2006-08-30 2008-03-13 Komori Corp 帯状体通し方法及びその装置

Also Published As

Publication number Publication date
JPS5892243A (ja) 1983-06-01

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