JPS62501321A - 超高純度重金属フッ化物の製造方法 - Google Patents

超高純度重金属フッ化物の製造方法

Info

Publication number
JPS62501321A
JPS62501321A JP60505334A JP50533485A JPS62501321A JP S62501321 A JPS62501321 A JP S62501321A JP 60505334 A JP60505334 A JP 60505334A JP 50533485 A JP50533485 A JP 50533485A JP S62501321 A JPS62501321 A JP S62501321A
Authority
JP
Japan
Prior art keywords
photoresist
layer
interlayer dielectric
metal
deposited
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60505334A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0320064B2 (enFirst
Inventor
リー，ウイリアム，ダブユ・ワイ
シヤウ，ガレス・エル
クレイトン，ジエームス・ダブユ
Original Assignee
ヒユ−ズ・エアクラフト・カンパニ−
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ヒユ−ズ・エアクラフト・カンパニ− filed Critical ヒユ−ズ・エアクラフト・カンパニ−
Publication of JPS62501321A publication Critical patent/JPS62501321A/ja
Publication of JPH0320064B2 publication Critical patent/JPH0320064B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/093—Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts
    • H10W20/096—Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts by contacting with gases, liquids or plasmas
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/435—Cross-sectional shapes or dispositions of interconnections

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP60505334A 1984-12-07 1985-11-25 超高純度重金属フッ化物の製造方法 Granted JPS62501321A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US679506 1984-12-07
US06/679,506 US4592132A (en) 1984-12-07 1984-12-07 Process for fabricating multi-level-metal integrated circuits at high yields

Publications (2)

Publication Number Publication Date
JPS62501321A true JPS62501321A (ja) 1987-05-21
JPH0320064B2 JPH0320064B2 (enFirst) 1991-03-18

Family

ID=24727173

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60505334A Granted JPS62501321A (ja) 1984-12-07 1985-11-25 超高純度重金属フッ化物の製造方法

Country Status (6)

Country Link
US (1) US4592132A (enFirst)
EP (1) EP0204768B1 (enFirst)
JP (1) JPS62501321A (enFirst)
KR (1) KR900001986B1 (enFirst)
DE (1) DE3570555D1 (enFirst)
WO (1) WO1986003622A1 (enFirst)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6087267A (en) * 1986-03-04 2000-07-11 Motorola, Inc. Process for forming an integrated circuit
US4786962A (en) * 1986-06-06 1988-11-22 Hewlett-Packard Company Process for fabricating multilevel metal integrated circuits and structures produced thereby
US4700462A (en) * 1986-10-08 1987-10-20 Hughes Aircraft Company Process for making a T-gated transistor
US4747211A (en) * 1987-02-09 1988-05-31 Sheldahl, Inc. Method and apparatus for preparing conductive screened through holes employing metallic plated polymer thick films
US5298365A (en) 1990-03-20 1994-03-29 Hitachi, Ltd. Process for fabricating semiconductor integrated circuit device, and exposing system and mask inspecting method to be used in the process
US5897376A (en) * 1993-09-20 1999-04-27 Seiko Instruments Inc. Method of manufacturing a semiconductor device having a reflection reducing film
TW439118B (en) * 2000-02-10 2001-06-07 Winbond Electronics Corp Multilayer thin photoresist process
US6713395B2 (en) * 2001-05-15 2004-03-30 Infineon Technologies Ag Single RIE process for MIMcap top and bottom plates
US6979526B2 (en) * 2002-06-03 2005-12-27 Infineon Technologies Ag Lithography alignment and overlay measurement marks formed by resist mask blocking for MRAMs
US7223612B2 (en) * 2004-07-26 2007-05-29 Infineon Technologies Ag Alignment of MTJ stack to conductive lines in the absence of topography
US7442624B2 (en) * 2004-08-02 2008-10-28 Infineon Technologies Ag Deep alignment marks on edge chips for subsequent alignment of opaque layers
JP2006261434A (ja) * 2005-03-17 2006-09-28 L'air Liquide Sa Pour L'etude & L'exploitation Des Procede S Georges Claude シリコン酸化膜の形成方法
TWI797640B (zh) 2020-06-18 2023-04-01 法商液態空氣喬治斯克勞帝方法研究開發股份有限公司 基於矽之自組裝單層組成物及使用該組成物之表面製備

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS494261A (enFirst) * 1972-05-01 1974-01-16

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3985597A (en) * 1975-05-01 1976-10-12 International Business Machines Corporation Process for forming passivated metal interconnection system with a planar surface
US4176029A (en) * 1978-03-02 1979-11-27 Sperry Rand Corporation Subminiature bore and conductor formation
GB1596907A (en) * 1978-05-25 1981-09-03 Fujitsu Ltd Manufacture of semiconductor devices
JPS5850417B2 (ja) * 1979-07-31 1983-11-10 富士通株式会社 半導体装置の製造方法
US4409319A (en) * 1981-07-15 1983-10-11 International Business Machines Corporation Electron beam exposed positive resist mask process
US4398964A (en) * 1981-12-10 1983-08-16 Signetics Corporation Method of forming ion implants self-aligned with a cut
CA1169022A (en) * 1982-04-19 1984-06-12 Kevin Duncan Integrated circuit planarizing process
FR2537779B1 (fr) * 1982-12-10 1986-03-14 Commissariat Energie Atomique Procede de positionnement d'un trou de contact electrique entre deux lignes d'interconnexion d'un circuit integre
DE3344280A1 (de) * 1982-12-21 1984-07-05 Texas Instruments Inc., Dallas, Tex. Verfahren zur herstellung einer halbleitervorrichtung und vorrichtung zur durchfuehrung des verfahrens
US4415606A (en) * 1983-01-10 1983-11-15 Ncr Corporation Method of reworking upper metal in multilayer metal integrated circuits
US4517731A (en) * 1983-09-29 1985-05-21 Fairchild Camera & Instrument Corporation Double polysilicon process for fabricating CMOS integrated circuits

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS494261A (enFirst) * 1972-05-01 1974-01-16

Also Published As

Publication number Publication date
JPH0320064B2 (enFirst) 1991-03-18
EP0204768A1 (en) 1986-12-17
DE3570555D1 (en) 1989-06-29
KR900001986B1 (ko) 1990-03-30
US4592132A (en) 1986-06-03
WO1986003622A1 (en) 1986-06-19
EP0204768B1 (en) 1989-05-24
KR870700171A (ko) 1987-03-14

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