JPS6232560B2 - - Google Patents

Info

Publication number
JPS6232560B2
JPS6232560B2 JP56097589A JP9758981A JPS6232560B2 JP S6232560 B2 JPS6232560 B2 JP S6232560B2 JP 56097589 A JP56097589 A JP 56097589A JP 9758981 A JP9758981 A JP 9758981A JP S6232560 B2 JPS6232560 B2 JP S6232560B2
Authority
JP
Japan
Prior art keywords
memory
address
chip
test
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56097589A
Other languages
English (en)
Japanese (ja)
Other versions
JPS581894A (ja
Inventor
Shuichi Fuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56097589A priority Critical patent/JPS581894A/ja
Publication of JPS581894A publication Critical patent/JPS581894A/ja
Publication of JPS6232560B2 publication Critical patent/JPS6232560B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/20—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits using counters or linear-feedback shift registers [LFSR]

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
JP56097589A 1981-06-25 1981-06-25 メモリのテスト方法 Granted JPS581894A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56097589A JPS581894A (ja) 1981-06-25 1981-06-25 メモリのテスト方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56097589A JPS581894A (ja) 1981-06-25 1981-06-25 メモリのテスト方法

Publications (2)

Publication Number Publication Date
JPS581894A JPS581894A (ja) 1983-01-07
JPS6232560B2 true JPS6232560B2 (enrdf_load_stackoverflow) 1987-07-15

Family

ID=14196420

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56097589A Granted JPS581894A (ja) 1981-06-25 1981-06-25 メモリのテスト方法

Country Status (1)

Country Link
JP (1) JPS581894A (enrdf_load_stackoverflow)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61108344A (ja) * 1984-10-31 1986-05-27 Hoshino Bussan Kk 早茄でにしてかつ強固な食感を有する乾燥麺類の製法及びその装置
WO2005017915A1 (ja) * 2003-08-18 2005-02-24 Fujitsu Limited 記憶装置および記憶装置の試験方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4404519A (en) * 1980-12-10 1983-09-13 International Business Machine Company Testing embedded arrays in large scale integrated circuits

Also Published As

Publication number Publication date
JPS581894A (ja) 1983-01-07

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