JPS62178575U - - Google Patents
Info
- Publication number
- JPS62178575U JPS62178575U JP6706186U JP6706186U JPS62178575U JP S62178575 U JPS62178575 U JP S62178575U JP 6706186 U JP6706186 U JP 6706186U JP 6706186 U JP6706186 U JP 6706186U JP S62178575 U JPS62178575 U JP S62178575U
- Authority
- JP
- Japan
- Prior art keywords
- component mounting
- electronic component
- soldering
- solder resist
- conductive foil
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005476 soldering Methods 0.000 claims description 4
- 239000011888 foil Substances 0.000 claims description 3
- 229910000679 solder Inorganic materials 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 2
- 238000000034 method Methods 0.000 claims 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Description
第１図はこの考案の一実施例を示す部分平面図
、第２図は従来の印刷配線板を示す部分平面図で
ある。
図において、１は絶縁基板、２は銅箔（導電箔
）パターン、３は電子部品取付けランド、４はソ
ルダレジストである。５はそれの半田付け用窓で
ある。図中同一符号は同一或は相当部分を示す。
FIG. 1 is a partial plan view showing an embodiment of this invention, and FIG. 2 is a partial plan view showing a conventional printed wiring board. In the figure, 1 is an insulating substrate, 2 is a copper foil (conductive foil) pattern, 3 is an electronic component mounting land, and 4 is a solder resist. 5 is its soldering window. The same reference numerals in the figures indicate the same or corresponding parts.
Claims (1)
導電箔パターンを形成し、上記電子部品取付けラ
ンドに電子部品をリフロー法で半田付けを行なう
為の半田付け用窓を残してソルダーレジストを被
覆してなる印刷配線板において、上記導電箔パタ
ーンの電子部品取付けランドの大きさを上記ソル
ダレジストの半田付け用窓より大なるようにした
ことを特徴とする印刷配線板。 A conductive foil pattern having electronic component mounting lands is formed on an insulating substrate, and a solder resist is covered with a soldering window that is left for soldering electronic components to the electronic component mounting lands using a reflow method. A printed wiring board characterized in that the size of the electronic component mounting land of the conductive foil pattern is larger than the soldering window of the solder resist.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6706186U JPS62178575U (en) | 1986-04-30 | 1986-04-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6706186U JPS62178575U (en) | 1986-04-30 | 1986-04-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62178575U true JPS62178575U (en) | 1987-11-12 |
Family
ID=30905624
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6706186U Pending JPS62178575U (en) | 1986-04-30 | 1986-04-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62178575U (en) |
-
1986
- 1986-04-30 JP JP6706186U patent/JPS62178575U/ja active Pending
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