JPS6216552B2 - - Google Patents
Info
- Publication number
- JPS6216552B2 JPS6216552B2 JP54068947A JP6894779A JPS6216552B2 JP S6216552 B2 JPS6216552 B2 JP S6216552B2 JP 54068947 A JP54068947 A JP 54068947A JP 6894779 A JP6894779 A JP 6894779A JP S6216552 B2 JPS6216552 B2 JP S6216552B2
- Authority
- JP
- Japan
- Prior art keywords
- tab
- lead
- strain
- lead frame
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6894779A JPS55162251A (en) | 1979-06-04 | 1979-06-04 | Lead frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6894779A JPS55162251A (en) | 1979-06-04 | 1979-06-04 | Lead frame |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2866288A Division JPS63211661A (ja) | 1988-02-12 | 1988-02-12 | リードフレーム |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS55162251A JPS55162251A (en) | 1980-12-17 |
| JPS6216552B2 true JPS6216552B2 (cg-RX-API-DMAC7.html) | 1987-04-13 |
Family
ID=13388359
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6894779A Granted JPS55162251A (en) | 1979-06-04 | 1979-06-04 | Lead frame |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS55162251A (cg-RX-API-DMAC7.html) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4791472A (en) * | 1985-09-23 | 1988-12-13 | Hitachi, Ltd. | Lead frame and semiconductor device using the same |
| JPS63148670A (ja) * | 1986-12-12 | 1988-06-21 | Texas Instr Japan Ltd | リ−ドフレ−ム材 |
| JPH0549806U (ja) * | 1991-12-16 | 1993-07-02 | 住友ゴム工業株式会社 | 舗装用弾性ブロック |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5144642Y2 (cg-RX-API-DMAC7.html) * | 1973-08-07 | 1976-10-29 | ||
| JPS53105175A (en) * | 1977-02-25 | 1978-09-13 | Hitachi Ltd | Lead frame for resin sealing semiconductor device |
-
1979
- 1979-06-04 JP JP6894779A patent/JPS55162251A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS55162251A (en) | 1980-12-17 |
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