JPS55162251A - Lead frame - Google Patents
Lead frameInfo
- Publication number
- JPS55162251A JPS55162251A JP6894779A JP6894779A JPS55162251A JP S55162251 A JPS55162251 A JP S55162251A JP 6894779 A JP6894779 A JP 6894779A JP 6894779 A JP6894779 A JP 6894779A JP S55162251 A JPS55162251 A JP S55162251A
- Authority
- JP
- Japan
- Prior art keywords
- tab
- leads
- sides
- joints
- distortion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
PURPOSE:To increase distortion absorbing effect by the method wherein a distortion absorbing through hole is provided on the joint between a tab for fastening a semiconductor chip and a tab lead for connecting this to an outer frame, and at the same time, the joints on both sides of the through hole are made symmetrical with respect to the center axis of the tab lead. CONSTITUTION:Tab leads 8 are made to project from the center of both sides of tab 5 for fastening IC chip 6. In parallel to these on both sides of leads 8, leads 4 for leading out electrodes are provided. In this lead frame so constructed, usually through holes 9 for absorbing distortion are provided at the parts where the ends of leads 8 come into contact with the outer frame of frame 2. In this device, these are not provided here. Instead, they are formed on the joints with tab 5, and at the same time, the joints on both sides of through holes 9 are made symmetrical with respect to the center axis of leads 8. By this, distortion absorbing effect is increased and no deviation occurs for the tab.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6894779A JPS55162251A (en) | 1979-06-04 | 1979-06-04 | Lead frame |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6894779A JPS55162251A (en) | 1979-06-04 | 1979-06-04 | Lead frame |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2866288A Division JPS63211661A (en) | 1988-02-12 | 1988-02-12 | Lead frame |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS55162251A true JPS55162251A (en) | 1980-12-17 |
JPS6216552B2 JPS6216552B2 (en) | 1987-04-13 |
Family
ID=13388359
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6894779A Granted JPS55162251A (en) | 1979-06-04 | 1979-06-04 | Lead frame |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS55162251A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4791472A (en) * | 1985-09-23 | 1988-12-13 | Hitachi, Ltd. | Lead frame and semiconductor device using the same |
US4870474A (en) * | 1986-12-12 | 1989-09-26 | Texas Instruments Incorporated | Lead frame |
JPH0549806U (en) * | 1991-12-16 | 1993-07-02 | 住友ゴム工業株式会社 | Elastic blocks for paving |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5039102U (en) * | 1973-08-07 | 1975-04-22 | ||
JPS53105175A (en) * | 1977-02-25 | 1978-09-13 | Hitachi Ltd | Lead frame for resin sealing semiconductor device |
-
1979
- 1979-06-04 JP JP6894779A patent/JPS55162251A/en active Granted
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5039102U (en) * | 1973-08-07 | 1975-04-22 | ||
JPS53105175A (en) * | 1977-02-25 | 1978-09-13 | Hitachi Ltd | Lead frame for resin sealing semiconductor device |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4791472A (en) * | 1985-09-23 | 1988-12-13 | Hitachi, Ltd. | Lead frame and semiconductor device using the same |
US4870474A (en) * | 1986-12-12 | 1989-09-26 | Texas Instruments Incorporated | Lead frame |
JPH0549806U (en) * | 1991-12-16 | 1993-07-02 | 住友ゴム工業株式会社 | Elastic blocks for paving |
Also Published As
Publication number | Publication date |
---|---|
JPS6216552B2 (en) | 1987-04-13 |
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