JPS6215850A - マルチチツプパツケ−ジ基板 - Google Patents

マルチチツプパツケ−ジ基板

Info

Publication number
JPS6215850A
JPS6215850A JP60154515A JP15451585A JPS6215850A JP S6215850 A JPS6215850 A JP S6215850A JP 60154515 A JP60154515 A JP 60154515A JP 15451585 A JP15451585 A JP 15451585A JP S6215850 A JPS6215850 A JP S6215850A
Authority
JP
Japan
Prior art keywords
substrate
silicon
oxide film
silicon oxide
chip package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60154515A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0464467B2 (enrdf_load_html_response
Inventor
Katsuzo Uenishi
上西　勝三
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP60154515A priority Critical patent/JPS6215850A/ja
Publication of JPS6215850A publication Critical patent/JPS6215850A/ja
Publication of JPH0464467B2 publication Critical patent/JPH0464467B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
    • H05K1/053—Insulated conductive substrates, e.g. insulated metal substrate the metal substrate being covered by an inorganic insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Waveguides (AREA)
JP60154515A 1985-07-13 1985-07-13 マルチチツプパツケ−ジ基板 Granted JPS6215850A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60154515A JPS6215850A (ja) 1985-07-13 1985-07-13 マルチチツプパツケ−ジ基板

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60154515A JPS6215850A (ja) 1985-07-13 1985-07-13 マルチチツプパツケ−ジ基板

Publications (2)

Publication Number Publication Date
JPS6215850A true JPS6215850A (ja) 1987-01-24
JPH0464467B2 JPH0464467B2 (enrdf_load_html_response) 1992-10-15

Family

ID=15585939

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60154515A Granted JPS6215850A (ja) 1985-07-13 1985-07-13 マルチチツプパツケ−ジ基板

Country Status (1)

Country Link
JP (1) JPS6215850A (enrdf_load_html_response)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03131056A (ja) * 1989-10-17 1991-06-04 Toshiba Corp 樹脂封止半導体装置
EP0685857A1 (en) * 1994-06-03 1995-12-06 Plessey Semiconductors Limited Inductor chip device
US5747870A (en) * 1994-06-30 1998-05-05 Plessey Semiconductors Limited Multi-chip module inductor structure
US6444499B1 (en) * 2000-03-30 2002-09-03 Amkor Technology, Inc. Method for fabricating a snapable multi-package array substrate, snapable multi-package array and snapable packaged electronic components

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03131056A (ja) * 1989-10-17 1991-06-04 Toshiba Corp 樹脂封止半導体装置
EP0685857A1 (en) * 1994-06-03 1995-12-06 Plessey Semiconductors Limited Inductor chip device
US5747870A (en) * 1994-06-30 1998-05-05 Plessey Semiconductors Limited Multi-chip module inductor structure
US6444499B1 (en) * 2000-03-30 2002-09-03 Amkor Technology, Inc. Method for fabricating a snapable multi-package array substrate, snapable multi-package array and snapable packaged electronic components

Also Published As

Publication number Publication date
JPH0464467B2 (enrdf_load_html_response) 1992-10-15

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Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term