JPS621278B2 - - Google Patents

Info

Publication number
JPS621278B2
JPS621278B2 JP4950479A JP4950479A JPS621278B2 JP S621278 B2 JPS621278 B2 JP S621278B2 JP 4950479 A JP4950479 A JP 4950479A JP 4950479 A JP4950479 A JP 4950479A JP S621278 B2 JPS621278 B2 JP S621278B2
Authority
JP
Japan
Prior art keywords
wiring board
leadless
printed wiring
resin
printing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP4950479A
Other languages
English (en)
Japanese (ja)
Other versions
JPS55141734A (en
Inventor
Eiichi Tsunashima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP4950479A priority Critical patent/JPS55141734A/ja
Publication of JPS55141734A publication Critical patent/JPS55141734A/ja
Publication of JPS621278B2 publication Critical patent/JPS621278B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Apparatuses And Processes For Manufacturing Resistors (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
JP4950479A 1979-04-20 1979-04-20 Method for coating leadless part installed on printed circuit board Granted JPS55141734A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4950479A JPS55141734A (en) 1979-04-20 1979-04-20 Method for coating leadless part installed on printed circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4950479A JPS55141734A (en) 1979-04-20 1979-04-20 Method for coating leadless part installed on printed circuit board

Publications (2)

Publication Number Publication Date
JPS55141734A JPS55141734A (en) 1980-11-05
JPS621278B2 true JPS621278B2 (ko) 1987-01-12

Family

ID=12832958

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4950479A Granted JPS55141734A (en) 1979-04-20 1979-04-20 Method for coating leadless part installed on printed circuit board

Country Status (1)

Country Link
JP (1) JPS55141734A (ko)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58204546A (ja) * 1982-05-25 1983-11-29 Citizen Watch Co Ltd Icの封止方法
JPH07107952B2 (ja) * 1985-09-19 1995-11-15 株式会社日立製作所 電子回路板
JPH0695594B2 (ja) * 1989-02-03 1994-11-24 日本レック株式会社 電気配線基板の表面実装に於ける電気部品の樹脂封止方法
JP2008288250A (ja) * 2007-05-15 2008-11-27 Nec Electronics Corp マルチチップパッケージ

Also Published As

Publication number Publication date
JPS55141734A (en) 1980-11-05

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