JPS62126456A - 並列演算処理装置 - Google Patents
並列演算処理装置Info
- Publication number
- JPS62126456A JPS62126456A JP26504285A JP26504285A JPS62126456A JP S62126456 A JPS62126456 A JP S62126456A JP 26504285 A JP26504285 A JP 26504285A JP 26504285 A JP26504285 A JP 26504285A JP S62126456 A JPS62126456 A JP S62126456A
- Authority
- JP
- Japan
- Prior art keywords
- arithmetic
- processing unit
- central processing
- response
- unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Multi Processors (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26504285A JPS62126456A (ja) | 1985-11-27 | 1985-11-27 | 並列演算処理装置 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26504285A JPS62126456A (ja) | 1985-11-27 | 1985-11-27 | 並列演算処理装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62126456A true JPS62126456A (ja) | 1987-06-08 |
| JPH051505B2 JPH051505B2 (OSRAM) | 1993-01-08 |
Family
ID=17411773
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26504285A Granted JPS62126456A (ja) | 1985-11-27 | 1985-11-27 | 並列演算処理装置 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62126456A (OSRAM) |
-
1985
- 1985-11-27 JP JP26504285A patent/JPS62126456A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH051505B2 (OSRAM) | 1993-01-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5784647A (en) | Interface for fetching highest priority demand from priority queue, predicting completion within time limitation then issuing demand, else adding demand to pending queue or canceling | |
| US5056011A (en) | Direct memory access controller with expedited error control | |
| US5321400A (en) | Serial data interface circuit dealing with a plurality of receiving modes | |
| US6330629B1 (en) | Information processing system | |
| JPS62126456A (ja) | 並列演算処理装置 | |
| JPH1063617A (ja) | シリアル通信装置 | |
| JPH0385660A (ja) | 入出力制御システム | |
| JP2638505B2 (ja) | バスインタフェース装置 | |
| JP2667285B2 (ja) | 割込制御装置 | |
| JP3442099B2 (ja) | データ転送記憶装置 | |
| JPS63205726A (ja) | マイクロコンピユ−タ | |
| JPH01318140A (ja) | マルチプロセッサシステム | |
| JPH0248762A (ja) | コンピュータ・システム | |
| JPH07334453A (ja) | メモリアクセスシステム | |
| JPH06348378A (ja) | レジスタ未使用ビット処理回路 | |
| JPS5831437A (ja) | デ−タ受信装置 | |
| JPS62145345A (ja) | 直接メモリアクセス間隔制御方式 | |
| JPS6340956A (ja) | デ−タ転送装置 | |
| JPS6368954A (ja) | 情報転送方式 | |
| JPH05143531A (ja) | データ処理装置 | |
| JPS6340955A (ja) | 直接メモリアクセス制御装置 | |
| JPS61241856A (ja) | レジスタの割込解除方式 | |
| JPH06175972A (ja) | バスシステム | |
| JPH0380359A (ja) | プロセッサ間通信方式 | |
| JPH08272735A (ja) | 情報処理装置 |