JPS62126456A - Parallel arithmetic processor - Google Patents

Abstract

PURPOSE:To speed up a processing by providing an I/O control circuit and a first in/first out (FEFO) memory. CONSTITUTION:Under the conditions that arithmetic units 3a-3d are in idle status, other arithmetic units having units Nos. smaller than the arithmetic units 3a-3d are not in idle status and an arithmetic result output permission signal 31 is not outputted from a central processor 1, an I/O circuit for discriminating a response outputs a response signal from a specified arithmetic unit and the FIFO memory 5 stores the units No. of the arithmetic unit generating the response signal at the reception of the response signal and forms an output request signal based on a compared result between the stored units No. and the units No. of the arithmetic unit at the transmission of data. Consequently, the processing speed can be increased.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a parallel arithmetic processing device that transfers and processes data to be computed by giving an arithmetic execution command from a central processing unit to one of arithmetic devices having the same function. Regarding.

[Conventional technology]

FIG. 4 is a block connection diagram showing a conventional parallel arithmetic processing device disclosed in, for example, Japanese Unexamined Patent Publication No. 57-143670). In the figure, 1 is a central processing unit, 2 is a common control unit, and 3 a * 3 b is an arithmetic device with the same function, 1
01 is a data bus connecting the central processing unit 1 and the common control unit 2, 102 is a control line between the central processing unit 1 and the common control unit 2, and 103 and 104 are respective lines where the common control unit 2 selects the arithmetic unit 3aa3b. selection lines 105 and 106 are status display lines 107 for conveying the status of the arithmetic units 3a+3b to the common control unit 2;
is a data bus connecting the common control unit 2 and the arithmetic units 3a+3b.

Next, the operation will be explained.

First, the central processing unit 1 transfers data to be processed by the arithmetic units 3 a # 3 b and a command instructing the sending of this data to the common control unit 2 via the data bus 101 and the control line 102 . The common control unit 2 is the central processing unit 1
Each time a command is sent from
Referring to the status report of each arithmetic device 3a+3b sent from 06, select arithmetic device 3aeab that is not in operation and that has not issued a request to output the arithmetic result via selection line 103.104. Select one from. now,
If the arithmetic device 13a is selected, the common control device 2
transfers data to the arithmetic unit 3a via the data bus 107 and instructs it to execute an arithmetic operation. Thereby, the arithmetic device 3
a reports the status of the computation operation to the common control device 2 via the status display line 105, and then starts the computation. After the computation is completed, the computation device 3a cancels the previously transmitted status of the computation in progress to the common control device 2 via the status display line 105, making it possible to accept the next command.

When the central processing unit 1 completes the transfer of all calculation data or when a request for output of the calculation results is issued from the calculation units 3a and 3b, the central processing unit 1 issues a common command specifying the calculation unit number from which the calculation results are to be read. Data bus 1 to control device 2
01 and the control line 102. Common control device 2
selects one of the designated arithmetic units 3a, 3b and instructs the arithmetic unit to read via the data bus 107. At this time, if the common control device 2 receives a report via the status display line that the arithmetic unit is in operation, it waits for the selection operation until the in-operation status is canceled.

[Problem that the invention seeks to solve]

Since the conventional parallel arithmetic processing device is configured as described above, in the common control device 2, all the arithmetic devices 3as3
It is necessary to monitor and control the state of b, arithmetic unit 3ae
If the number of units 3b increases, the control mechanism becomes complicated, and the common control unit 2 is interposed between the central processing unit 1 and the arithmetic units 3a and 3b, which causes overhead. When outputting the calculation result from *3b, it is necessary to specify the number of the calculation unit 3a*3b in the central processing unit 1, which poses a problem in that the overall performance cannot be sufficiently increased.

This invention was made in order to solve the above-mentioned problems. Each arithmetic unit connected in parallel monitors each other's status, and in response to arithmetic requests issued from the central processing unit, the arithmetic units In addition to determining the arithmetic unit that will return the response, the data is output in the order of the arithmetic units that received the data, without requiring many procedures in the central processing unit when sending the arithmetic results back to the central processing unit. The purpose of this invention is to obtain a parallel arithmetic processing device.

[Means for solving problems]

The parallel arithmetic processing device according to the present invention has an input/output control circuit for determining a response in response to an arithmetic request from the central processing unit.
Whether or not a computing device accepts the request and responds is determined based on the state of each computing device itself, a comparison of preset device numbers with other computing devices in an idle state, and the usage status of the data bus. The device number of the arithmetic device that has determined the response is stored in a first-in/first-out memory provided in the central processing unit.

[For production]

The input/output circuit for response determination in the present invention is configured such that when the arithmetic unit is in an idle state, no other arithmetic unit with a smaller device number than that arithmetic unit is in an idle state, and the central processing unit gives permission to output the arithmetic result. Provided that no signal is being output and that no other arithmetic device is outputting a response signal, the specified arithmetic device will output a response signal, and the first-in/first-out memory will output the response signal when the first-in/first-out memory has received the above response signal. At this time, the device number of the arithmetic device that issued this response signal is stored, and the result of comparing this stored device number with the device number of the arithmetic device at the time of data transmission is used to form an output request signal. .

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 1 is a central processing unit for control, 3a, 3b
, 3c e3d is an arithmetic unit with the same functions, 4a+
4b +4c o4d is an input/output control device for the arithmetic units 3a to 3d; 5 is a first-in/first-out memory provided in the central processing unit 1; 101 is a data bus;
2 is a control line. The control line 102 connects each arithmetic device 3a to 3.
It is common in d.

FIG. 2 shows a specific embodiment of the input control section in the input/output control devices 4a to 4d shown in FIG. 10.11 is a label signal indicating a device number fixedly determined by the mounting position of the arithmetic device, 12 is a decoder, and 13 is an input ready signal indicating the idle state of the arithmetic device, which is an enable signal for the decoder 12. 14゜15.16.17 are decoded signals obtained by decoding the label signal, 18, 19, 20.21
are status display lines in which the decoded signals 14 to 17 obtained by decoding the label signals of each arithmetic unit are wired with 0, 22, 23, 24 are signals fed back the upper 3 bits of the status display lines 18 to 21, and 25 is a signal obtained by feeding back the upper 3 bits of the status display lines 18 to 21. A calculation request signal 26 is issued from the control central processing unit, and a state determination circuit 26 outputs a response signal 27 in response to the calculation request signal.

28 is the first timing signal, 29 is the second timing signal, and 30 is the response signal 27 as the second timing signal 29.
The sampled signal 31 is a calculation result output permission signal issued from the central processing unit 1 for control.

FIG. 3 is a circuit diagram of the output control section in the input/output control devices 3a to 3d in FIG. 1! +, 41.42 are the output signals of the first-in/first-out memory 5 in the control central processing unit 1, and 43 are the label signals 10.11 and the output signals 41.11 of the first-in/first-out memory 5 in FIG. 42 is a comparator that compares 42, 44 is an output ready signal indicating that the arithmetic unit is ready to output the arithmetic result, 45 is a request signal for outputting the arithmetic result to the control central processing unit IK, and 46 is a data bus output buffer control signal. It is.

Next, the operation will be explained.

Now, since there are four arithmetic devices 3a to 3d, the label signal (device number signal) of the arithmetic devices 3a to 3d is 10.11.
Divide @01.111.1+21 to the value of w3m. This value is fixed. Here, the device number is, for example, 12.
When the arithmetic unit mounted in position 1 is in the idle state, the input ready signal 13 is significant and the label signal 10.11
Of the decoded signals 14 to 17, only decoded signal 16 is significant; the following are meaningless. Further, when the arithmetic device is in operation, the input ready signal 13 is unexpectedly υ,
Decoder 12 is disabled and decoded signal 1
4 to 17 are all meaningless. Therefore, the decoded signal 14
.about.17 indicate whether each arithmetic device 3a-3d is in an idle state or not. When the calculation request signal 25 is received from the control central processing unit 1, a response signal 27 is sent from the calculation unit with the label mounted at this position as the first timing signal 2.
The conditions that are output in synchronization with 8 are as follows.

That is, ■ the arithmetic unit is in an idle state; (2) there is no arithmetic unit with a smaller label (equipment number) than the arithmetic unit in an idle state; and - the control central processing unit 1 has given permission to output the arithmetic results. The signal 31 is not being issued, and (2) the response signal 27 is not being issued by any other arithmetic device.

That is, (1) being in the output ready state; (2) output signals 41 and 42 of the first-in/first-out memory 5 in the control central processing unit 1 and the own label 10.
11 match, and (2) the output permission signal 31 is issued from the control central processing unit 1.

〔Effect of the invention〕

As described above, according to the present invention, the input/output circuit for response determination is configured such that the arithmetic device is in an idle state and that no other arithmetic device having a smaller device number than the arithmetic device is in an idle state. Provided that the central processing unit does not output a calculation result output permission signal and that no other calculation device outputs a response signal, the specified calculation device outputs a response signal and performs first-in/first-out. When the above response signal is received, the memory stores the device number of the arithmetic device that issued the response signal, and uses the comparison result between the stored device number and the device number of the arithmetic device at the time of data transmission to issue an output request. Since the configuration is configured to form a signal, it is possible to determine one arithmetic unit that can respond among the arithmetic units, and the output order of the arithmetic results can be determined without requiring many procedures in the central processing unit, increasing efficiency. Since it is possible to use the arithmetic unit in a flexible manner, the load on the central processing unit is also reduced, and as a result, the processing speed can be increased.

[Brief explanation of drawings]

FIG. 1 is a block connection diagram of a parallel arithmetic processing device according to an embodiment of the present invention, FIG. 2 is a block connection diagram of an input control section of an input/output control device, and FIG. 3 is a block connection diagram of an output control section. FIG. 4 is a block connection diagram of a conventional parallel arithmetic processing device. In the figure, l is the central processing unit, 2 is the common control unit, and 3 is the central processing unit.
a to 3d are arithmetic devices, 4 is an input/output control device in the arithmetic device, 5 is a first-in/first-out memory, 26
is the state judgment circuit. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] In a parallel arithmetic processing unit that transfers and processes data to be computed by giving an arithmetic execution command from a control central processing unit to one of a plurality of arithmetic units having the same function, in response to an arithmetic request from the central processing unit, , whether or not each computing device accepts this computing request and returns a response is determined by comparing its own status, the preset device number with other computing units that are in an idle state, and the usage status of the data bus. The first-in/first-out memory provided in the central processing unit stores an input/output control circuit for determining a response based on the response, and a first-in/first-out memory provided in the central processing unit for storing the device number of the arithmetic unit that has determined the response. Parallel processing unit.