JPH03271960A - Intelligent inter-cpu adapter - Google Patents

Abstract

PURPOSE:To make information transmission disability extremely hard to occur and to reduce the load of transmission processing on a CPU main body by providing plural link units and giving priority levels to the respective link units. CONSTITUTION:The inter-CPU adapter 2 has at least >=2 link units 4 - 6 having priority levels and a control unit 8 which controls the link units 4 - 6, and the control unit 8 judges the kind of information to be sent and the use states of the respective link units 4 - 6 totally to select and use one proper unit among the link units 4 - 6. Thus, the link units 4 - 6 are used flexibly to reduce the stop fault, etc., of the computer system due to a defect in information transmis sion between CPU devices, thereby drastically reducing the load on the CPU main body.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an inter-CPtJ coupling device having a plurality of link means.

[Prior Art] Conventionally, when connecting two CPU devices, a method has been used in which a plurality of link units of the same hardware are prepared and information to be transmitted and received is associated with a specific link unit.

[Section M where the invention is about to be decided N] In the conventional technology, for example, among two link units,
If a problem occurs with the first link unit and it becomes unusable, it is common to notify the user that an abnormality has occurred in the first link unit and call for attention. Therefore, there is no way to actively use the second link unit to transmit information that should be transmitted by the first link unit, and important information cannot be transmitted to the other party's CPU device, resulting in a system stoppage. There was a point between the two.

[Means for Solving the Problems] In order to solve the problem like a queen, the present invention provides an intelligent inter-CPU coupling device that has a plurality of link units and has 8 priority levels for each link unit. With the goal.

[Operations] In the inridient CPU I'i51 device according to the present invention, by flexibly using a plurality of link units, it is possible to reduce computer system stop failures caused by transmission failures in information transmission between CPU devices. The load on the CPIJ body can be significantly reduced by 11.

[Embodiment] Figure 1 shows a configuration diagram of a computer system comprising two CPU devices according to the present invention.

The CPU bodies 1a and 1b are each intelligent CPUs.
It is connected to the U-to-U coupling devices 2a and 2b (the part surrounded by the dotted line) by buses A and B. Also, intelligent C
Inside the inter-PU coupling devices 2a and 2b, the internal bus 3a
and 3b, the control units 8a and 8b are connected to the link parts 7a and 7b (the part surrounded by the - dotted line M).

Three link units 4a, 5a, 6a and 4b, 5b, 6b are housed inside links g57a and 7b, respectively, and 4a and 4bs5 are housed inside links g57a and 7b.
a and 5b, 6a and 6b are transmission cables 4c and 5, respectively.
c and 6c.

In this embodiment, the transmission cables 4c, 5c6C are all electrical signal cables, but some or all of them may be optical signal cables.

Next, focusing on the intelligent CPt-T coupling device 2a, its Φ masterpiece will be explained.

The control unit 8a is mainly composed of a 16-bit processor, and the internal bus 3a is a bus that can handle 16-bit parallel data and is connected to the link unit 4a*.
5a and 6a are connected to the internal bus 3a-, respectively. Link unit 4a.

Both 5a and 6a perform parallel/serial conversion internally, and the data given from the CPU main body 1a is converted into 16-bit parallel data by the control unit 8a, and this parallel data is converted into serial data. The signal is output (transmitted) to the transmission cable 4C5c+6c.

Conversely, transmission cable 4 c s 5 c s 6 c
The serial data input (received) from the controller is transformed into parallel data and sent to the control unit 8 via the internal bus 3a.
a, then the CPU main body 1a.

In addition, link units 4 a + 5 a s 6
a includes a transmission speed setting circuit that sets the transmission speed, an address determination circuit that determines which link unit is designated by the control unit 8a, and a priority setting circuit that sets priorities among the 8 link units. , an interface circuit with the internal bus 3a, and a status register that indicates whether the 8-link unit is in use, whether an abnormality has occurred, the amount of load, etc.

A block diagram of this link unit is shown in FIG.

In this embodiment, link unit 4 a s 5 a *
The following settings are made for 6a, 4b, 5b, and 5b.

Pp, the link units 4a and 4b have a transmission speed of 102
4 kbps, priority 1. link unit 5
a and 5b have a transmission speed of 512 kbps and a priority of 2. Link unit 5a s 6b has a transmission speed of 512
k b p s s m priority order 3 are given here, and the priority order (ff is "1" is the highest, then "
2", and the lowest one is "3".

Next, the control units 8a*8b and the link part 7a7
Let me explain about b's masterpiece.

The control unit 8a connects the link part 7 via the link part 7a.
b. An example of transmitting information to the control unit 8b will be explained.

The control unit 8a performs two main operations depending on whether the information to be transmitted is "emergency information" (for example, information about the occurrence of a power outage) or "normal information" (for example, arbitrary data). This situation is shown in Figure 3.

When attempting to transmit "emergency information", the control unit 8a sets the address of the link unit 4a with the highest priority, reads the contents of the status register of the link unit 4a, and allows the link unit 4a to transmit. If so, information is set on the internal bus 3a and a transmission command is given.

At this time, in the status register of link unit 4a,
For example, if "abnormality occurrence" is set, the control unit 8a will control the link unit 5a with the next highest priority.
, and performs the same process as that for the link unit 4a. Again, if it is determined that link unit 5a is unable to transmit, similar processing is performed for link unit 6a as well.

In this respect, since the CPU-to-CPU coupling device 2a is occupied with the transmission process of "emergency information," the first information given to the other party's CPU-to-CPU coupling device 2b is "emergency information J." is transmitted with highest priority.

Conversely, when attempting to transmit "normal information", the control unit 8a transmits the link unit 6 with the lowest priority.
The contents of the status register of a are read out, and if the link unit 6a is capable of transmission, the information is set on the internal data bus 3a and a transmission command is given.

At this time, if, for example, "abnormality occurrence" is set in the status register of the link unit 6a, the control unit 8a will give the next highest priority or reset the address of the link unit 5a, and The status is read out, and the same process as that for the link unit 6a is performed.

Furthermore, if the link unit 5a is also unable to transmit, the transfer will be made to the link unit 4a.

Here, the link units 5a and 6a are also connected to the link unit 4.
If unit a is unavailable, the control unit 8
a is the link unit 5a, 6 when transmitting "emergency information".
In step a, even if some normal information J is waiting for its turn, the emergency information is processed by being preferentially interrupted by each link unit 5a, 6a.

On the other hand, the operation at the time of reception will be explained regarding the inter-CPtJ coupling device 2b.

In the intelligent inter-CPU coupling device 2b, the transmitted information is transmitted to each link unit 4b, 5 of the link section 7b.
It is set to either b or 6b.

As already explained, the link units 4b, 5b, and 6b have priorities, and an interrupt of a level corresponding to this priority is applied to the control unit 8b. The control unit 8b determines from which link unit information should be obtained based on this interrupt level, and performs read processing on the unit from which information is to be obtained. (Interrupt levels range from "1" to "3", with "1" being the highest and "3" being the highest.
” is the lowest) As a result, even if received information occurs simultaneously on the surfaces of three link units 4b, 5b, and 6b, the control unit 8b
This means that the information of the link unit with the highest priority can be processed in order.

This situation is shown in Figure 14.

As explained above, when the information to be transmitted is "emergency information", the link units 4a, 4 with high priority
(b) Reads out the false status, and if transmission is not possible, sequentially moves to the transmission with the highest priority, searches for the transmission that can be reliably transmitted from all of the link sections 7a and 7b, and transmits it. In the case of "normal information", link unit search is performed in reverse.

In addition, in the receiving operation, link units 4a, 4
b, 5as Processing is executed based on the priority order unique to 5b, 6a, and 6b.

[Effects of the Invention] According to the intelligent CPU-to-CPU coupling device according to the present invention, flexible operation using a plurality of link units is possible, and therefore information transmission failure is extremely unlikely to occur. Furthermore, the load on the CPU main body during transmission processing can be reduced.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a computer system consisting of two sets of intelligent CPυ coupling devices according to the present invention.
The figure is a block diagram of the link unit, Figure 3 is a flowchart when transmitting information, and Figure 4 is a flowchart when receiving information. la, 1b: C: PLJ main body 2a, 2b: C: PUE coupling device 4a, 4bs 5a, 5b, 6as 6b: Link unit 7 a s 7 b: Link part 8a, 8b: Control unit

Claims (1)

[Claims] A CPU main body and other CPUs connected to the CPU main body
In the inter-CPU coupling device used for communication with the device,
The inter-CPU coupling device has at least two
The control unit includes at least one set of link units and a control unit that controls the link units, and the control unit comprehensively determines the type of information to be transmitted and the usage status of each link unit, and controls the link units. An intelligent inter-CPU coupling device characterized in that an appropriate link unit set is selected and used from among the following.