JPS6211499B2 - - Google Patents

Info

Publication number
JPS6211499B2
JPS6211499B2 JP53128348A JP12834878A JPS6211499B2 JP S6211499 B2 JPS6211499 B2 JP S6211499B2 JP 53128348 A JP53128348 A JP 53128348A JP 12834878 A JP12834878 A JP 12834878A JP S6211499 B2 JPS6211499 B2 JP S6211499B2
Authority
JP
Japan
Prior art keywords
wire
pad
bonding
pellet
periphery
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP53128348A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5555541A (en
Inventor
Tamotsu Usami
Kanji Ootsuka
Yukiaki Ueno
Akira Masaki
Hiroki Yamashita
Tadao Kachi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP12834878A priority Critical patent/JPS5555541A/ja
Priority to DE19792942394 priority patent/DE2942394A1/de
Publication of JPS5555541A publication Critical patent/JPS5555541A/ja
Publication of JPS6211499B2 publication Critical patent/JPS6211499B2/ja
Granted legal-status Critical Current

Links

Classifications

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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP12834878A 1978-10-20 1978-10-20 Semiconductor element Granted JPS5555541A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP12834878A JPS5555541A (en) 1978-10-20 1978-10-20 Semiconductor element
DE19792942394 DE2942394A1 (de) 1978-10-20 1979-10-19 Halbleiteranordnung

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12834878A JPS5555541A (en) 1978-10-20 1978-10-20 Semiconductor element

Publications (2)

Publication Number Publication Date
JPS5555541A JPS5555541A (en) 1980-04-23
JPS6211499B2 true JPS6211499B2 (enrdf_load_stackoverflow) 1987-03-12

Family

ID=14982579

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12834878A Granted JPS5555541A (en) 1978-10-20 1978-10-20 Semiconductor element

Country Status (2)

Country Link
JP (1) JPS5555541A (enrdf_load_stackoverflow)
DE (1) DE2942394A1 (enrdf_load_stackoverflow)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2616964B1 (fr) * 1987-06-19 1990-03-02 Thomson Composants Militaires Puce de circuit integre avec plots d'entree-sortie allonges
US4959706A (en) * 1988-05-23 1990-09-25 United Technologies Corporation Integrated circuit having an improved bond pad
JP2768822B2 (ja) * 1990-11-29 1998-06-25 株式会社東芝 ワイヤボンディグ方式半導体装置
US5404047A (en) * 1992-07-17 1995-04-04 Lsi Logic Corporation Semiconductor die having a high density array of composite bond pads
US5340772A (en) * 1992-07-17 1994-08-23 Lsi Logic Corporation Method of increasing the layout efficiency of dies on a wafer and increasing the ratio of I/O area to active area per die
US6262434B1 (en) * 1996-08-23 2001-07-17 California Micro Devices Corporation Integrated circuit structures and methods to facilitate accurate measurement of the IC devices
JP4523425B2 (ja) * 2005-01-12 2010-08-11 株式会社住友金属エレクトロデバイス 半導体素子搭載用基板
DE102008013756B4 (de) * 2008-03-12 2019-08-22 F&K Delvotec Bondtechnik Gmbh Verfahren und Drahtbonder zur Herstellung einer Golddraht-Bondverbindung

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3808475A (en) * 1972-07-10 1974-04-30 Amdahl Corp Lsi chip construction and method
CH592366A5 (enrdf_load_stackoverflow) * 1975-06-05 1977-10-31 Ebauches Sa

Also Published As

Publication number Publication date
DE2942394C2 (enrdf_load_stackoverflow) 1991-05-02
DE2942394A1 (de) 1980-05-08
JPS5555541A (en) 1980-04-23

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