JPS6188537A - 半導体装置のリ−ド - Google Patents

半導体装置のリ−ド

Info

Publication number
JPS6188537A
JPS6188537A JP59210007A JP21000784A JPS6188537A JP S6188537 A JPS6188537 A JP S6188537A JP 59210007 A JP59210007 A JP 59210007A JP 21000784 A JP21000784 A JP 21000784A JP S6188537 A JPS6188537 A JP S6188537A
Authority
JP
Japan
Prior art keywords
lead
wire
bonding
semiconductor device
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59210007A
Other languages
English (en)
Inventor
Saneyasu Hirota
弘田　実保
Yoko Shibuya
渋谷　洋子
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP59210007A priority Critical patent/JPS6188537A/ja
Publication of JPS6188537A publication Critical patent/JPS6188537A/ja
Pending legal-status Critical Current

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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明はＩＣやトランジスタ等の半導体装置のリード
に関するものである。
（従来の技術） 半導体チップの電極とリード端子とのワイヤボンディン
グには従来、金ワイヤが使用されていたが、金ワイヤの
価格が高いので、最近銅ワイヤを用いることが提案され
ている。また、リード端子は従来、銀めっきなどの表面
処理が施されていたが、銀めっきを省略し銅ワイヤを銅
合金リード上に直接接合することにより、二重の原価の
低下が達成される。
第４図は銅ワイヤを用いた超音波併用熱圧着ボンディン
グ方法によるワイヤボンディングの状態を示す断面図で
ある。図において、１はダイパッド、２は該ダイパッド
１０表面に装着された半導体チップ、３は該チップ２表
面に形成されたアルミニウム電極、４は半導体装置の銅
合金リード、５はセラミック製のキャピラリチップ、６
は２５μｍの直径φを有する銅ワイヤであり、これはキ
ャピラリチップ５を用いた超音波併用熱圧着ボンディン
グ方式によって、アルミニウム電極３の表面上にボール
ボンディングされ、次いで上記銅合金リード４表面にス
テッチボンディングされるものである。７はボンディン
グ時に上記リード４を固定するためのリード押さえであ
る。
超音波併用熱圧着ボンディングにおいて良好な接合状態
を得るためには、大気中で形成される材料表面の酸化被
膜などの吸着物を十分に破壊、除去すること、及び接合
界面における材料の微視的な塑性変形により、酸化膜破
壊後の新生面同士を原子間距離にまで密着させてそれら
の接触面積を拡大させることが極めて重要である。
〔発明が解決しようとする問題点〕 しかるに、従来の金ワイヤに替えて銅ワイヤ６を用い、
銀めっきを省略した銅合金リード４に直接ステッチボン
ディングを行う場合、上記の２点、即ち酸化被膜を除去
すること、接合界面での塑性変形を所望の変形にするこ
とが従来の材料の組合せよりも困難である。そのため、
ステッチボンディング部における接合不良、即ち接合強
度不足あるいはボンディング時におけるはがれなどが発
生するという問題点があった。
この発明は、このような問題点を解消するためになされ
たもので、ワイヤがボンディングされる際の接合不良を
防止できる半導体装置のリードを得ることを目的とする
ものである。
〔問題点を解決するための手段〕
この発明に係る半導体装置のリードは、該リードのボン
ディング表面に、接合時の超音波の振動方向に大きさの
等しい複数の鋸歯形状の溝を配列形成したものである。
〔作用〕
この発明においては、リードのボンディング表面に形成
された大きさの等しい複数の鋸歯形状の溝が該溝の山の
部分でワイヤ表面の吸着物を接合時の超音波の振動によ
り効率高く破壊、除去するから、ワイヤとリードの接合
界面における両者の微視的な塑性変形により吸着物破壊
後の新生面同士が原子間距離にまで密着しそれらの接触
面積が拡大される。
〔実施例〕
以下、この発明の実施例を図について説明する。
第１図（ａ）、　（ｂ）はそれぞれ本発明の一実施例に
よる半導体装置の表面加工された銅合金リードの上面、
側面を示す模式図である。
第１図おいて、１４はそのボンディング表面に、ボンデ
ィング時の超音波の振動方向に、大きさの等しい複数の
鋸歯形状の溝が配列形成されたＩＣ等の半導体装置の銅
合金リードであり、その溝は圧延ロールを用いて刻印、
又はエメリー紙でｇｆ磨することにより、加工ピッチａ
が超音波の振動振幅とほぼ同じの１μｍ、加工深さｂが
１．０〜１．５μｍ程度に加工形成されているものであ
る。また、第３図は加工深さｂと接合強度Ｓの関係を示
しているが、これより該深さｂが１．０〜１．５μｍ程
度の範囲で最も接合強度Ｓが高くなっているのが分かる
。
このような銅合金リードの表面加工によるステッチボン
ディングの接合性向上は以下のような原理に基づくもの
と推察される。
即ち、銅ワイヤ６及び銅合金リード１４の表面には、通
常吸着物である数十〜数百人の酸化膜が形成されており
、これらを破壊し、新生面を露出させることが接合の第
１段階となるが、銅ワイヤ６表面の酸化膜破壊に対して
、銅合金リード１４表面の形状２寸法が強く影響を与え
ると考えられる。
このため、銅合金リード１４の表面を接合時の超音波振
動の方向に振動振幅とほぼ１μｍの等ピッチで深さ１．
０〜１．５μｍの鋸歯状に加工して溝を形成することに
より、第２図に示すボンディングの際に、その山の部分
で銅ワイヤ６の表面酸化膜を効果的に破壊するためと推
察される。
また、第３図に示されているように溝の深さｂを１．５
μｍ以上にすると接合性が低下するのは、表面起伏が激
しくなると新生面露出後の該新生面同志を塑性変形によ
り原子間距離にまで密着させるという点で不利になるた
めと推察される。
このように本実施例の銅合金リード１４によれば、その
ボンディング表面をほぼ１μｍ間隔で深すカ１．０〜１
．５μｍの鋸歯状に加工したので、接合時に銅ワイヤ６
の表面酸化膜を効果的に破壊でき、該銅ワイヤ６と上記
銅合金リード１４の接合界面における材料の微視的な塑
性変形により、酸化膜破壊後の新生面同士が原子間距離
にまで密着し、それらの接触面積が拡大され、ステンチ
ボンディング部における接合不良がなくなり、良好な接
合状態を得ることができる。
なお上記実施例においては、φ２５μｍの銅ワイヤ６の
場合について説明したが、φ５ｏμｍ等他の線径にフい
ても同様な効果が期待される。
また上記実施例では、銅ワイヤ６及び銅合金リード１４
の組合せについて説明したが、大気中で表面に強固な酸
化膜が形成される他の材質の組合せにおいても同様な効
果が期待される。
〔発明の効果〕
以上のように、この発明に係る半導体装置のリードによ
れば、該リードのボンディング表面に接合時の超音波の
振動方向に大きさの等、しい複数の鋸歯形状の溝を形成
したので、接合時にワイヤ表面の吸着物を効率筋（破壊
できて該ワイヤとリードの接合界面における両者の微視
的な塑性変形により新生面同士の接触面積が拡大され、
ボンディングの接合性を大幅に向上できる効果がある。
【図面の簡単な説明】
第１図（８１は本発明の一実施例による銅合金リードの
模式平面図、第１図中）はその模式側面図、第２図は上
記実施例におけるワイヤボンディング状態を示す模式断
面図、第３図は上記実施例のリードの加工面の寸法−接
合強度特性図、第４図は従来のＩＣにおけるワイヤボン
ディング状態を示す模式断面図である。 ５・・・キャピラリチップ、６・・・銅ワイヤ、１４・
・・銅合金リード。 なお図中、同一符号は同−又は相当部分を示す。 第１図 第３図 ｂ（７１ｍ）

Claims (4)

    【特許請求の範囲】
  1. （１）キャピラリチップを用いた超音波併用熱圧着ボン
    ディング方式によってワイヤがボンディングされる半導
    体装置のリードにおいて、該リードのボンディング表面
    に、ボンディング時の上記超音波の振動方向に、大きさ
    の等しい複数の鋸歯形状の溝が配列形成されていること
    を特徴とする半導体装置のリード。
  2. （２）上記鋸歯形状の溝の幅をほぼ１μｍとし、該溝の
    深さを１．０〜１．５μｍとしたことを特徴とする特許
    請求の範囲第１項記載の半導体装置のリード。
  3. （３）上記鋸歯形状の溝は上記リード表面に圧延ロール
    を用いて刻印することにより形成されたものであること
    を特徴とする特許請求の範囲第１項または第２項記載の
    半導体装置のリード。
  4. （４）上記鋸歯形状の溝はリードのボンディング表面を
    エメリー紙で研磨することにより加工形成されたもので
    あることを特徴とする特許請求の範囲第１項または第２
    項記載の半導体装置のリード。
JP59210007A 1984-10-05 1984-10-05 半導体装置のリ−ド Pending JPS6188537A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59210007A JPS6188537A (ja) 1984-10-05 1984-10-05 半導体装置のリ−ド

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59210007A JPS6188537A (ja) 1984-10-05 1984-10-05 半導体装置のリ−ド

Publications (1)

Publication Number Publication Date
JPS6188537A true JPS6188537A (ja) 1986-05-06

Family

ID=16582293

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59210007A Pending JPS6188537A (ja) 1984-10-05 1984-10-05 半導体装置のリ−ド

Country Status (1)

Country Link
JP (1) JPS6188537A (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62265729A (ja) * 1986-05-14 1987-11-18 Hitachi Ltd 半導体装置
DE112015006047B4 (de) 2015-06-24 2019-07-04 Meiko Electronics Co., Ltd. Herstellungsverfahren für eine räumliche leiterplatte, räumliche leiterplatte und substrat für eine räumliche leiterplatte

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62265729A (ja) * 1986-05-14 1987-11-18 Hitachi Ltd 半導体装置
JPH0450741B2 (ja) * 1986-05-14 1992-08-17 Hitachi Ltd
DE112015006047B4 (de) 2015-06-24 2019-07-04 Meiko Electronics Co., Ltd. Herstellungsverfahren für eine räumliche leiterplatte, räumliche leiterplatte und substrat für eine räumliche leiterplatte

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