JPS6159516A - タイマ機構 - Google Patents

タイマ機構

Info

Publication number
JPS6159516A
JPS6159516A JP59181207A JP18120784A JPS6159516A JP S6159516 A JPS6159516 A JP S6159516A JP 59181207 A JP59181207 A JP 59181207A JP 18120784 A JP18120784 A JP 18120784A JP S6159516 A JPS6159516 A JP S6159516A
Authority
JP
Japan
Prior art keywords
timer
control
processing
cpu
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59181207A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0473167B2 (en:Method
Inventor
Toshiki Nakajima
俊樹 中島
Yasuo Doi
土井　泰雄
Toshio Shoji
敏夫 東海林
Yoshinobu Ikeda
池田　義伸
Yasuhiko Makiura
牧浦　泰彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Hitachi Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Original Assignee
Fujitsu Ltd
Hitachi Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Hitachi Ltd, NEC Corp, Nippon Telegraph and Telephone Corp filed Critical Fujitsu Ltd
Priority to JP59181207A priority Critical patent/JPS6159516A/ja
Publication of JPS6159516A publication Critical patent/JPS6159516A/ja
Publication of JPH0473167B2 publication Critical patent/JPH0473167B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Measurement Of Predetermined Time Intervals (AREA)
JP59181207A 1984-08-30 1984-08-30 タイマ機構 Granted JPS6159516A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59181207A JPS6159516A (ja) 1984-08-30 1984-08-30 タイマ機構

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59181207A JPS6159516A (ja) 1984-08-30 1984-08-30 タイマ機構

Publications (2)

Publication Number Publication Date
JPS6159516A true JPS6159516A (ja) 1986-03-27
JPH0473167B2 JPH0473167B2 (en:Method) 1992-11-20

Family

ID=16096700

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59181207A Granted JPS6159516A (ja) 1984-08-30 1984-08-30 タイマ機構

Country Status (1)

Country Link
JP (1) JPS6159516A (en:Method)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02252008A (ja) * 1988-08-19 1990-10-09 Motorola Inc マイクロプロセッサ
JP2000214274A (ja) * 1999-01-25 2000-08-04 Nec Eng Ltd タイムアウト優先処理タイマ回路
JP2009043256A (ja) * 2007-08-06 2009-02-26 Nuvoton Technology Corp 記憶装置のアクセス方法及び装置

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02252008A (ja) * 1988-08-19 1990-10-09 Motorola Inc マイクロプロセッサ
JP2000214274A (ja) * 1999-01-25 2000-08-04 Nec Eng Ltd タイムアウト優先処理タイマ回路
JP2009043256A (ja) * 2007-08-06 2009-02-26 Nuvoton Technology Corp 記憶装置のアクセス方法及び装置
US8285895B2 (en) 2007-08-06 2012-10-09 Winbond Electronics Corporation Handshake free sharing in a computer architecture

Also Published As

Publication number Publication date
JPH0473167B2 (en:Method) 1992-11-20

Similar Documents

Publication Publication Date Title
US4926318A (en) Micro processor capable of being connected with a coprocessor
US5754863A (en) System for downloading program code to a microprocessor operative as a slave to a master microprocessor
JPS6159516A (ja) タイマ機構
KR940011041B1 (ko) 마이크로컴퓨터
JPH01305460A (ja) プロセッサ間通信方式
KR850006742A (ko) 데이터 처리장치
JPS6285372A (ja) マルチプロセツサシステムにおけるコンペアアンドスワツプ方式
JPS63240663A (ja) プロセツサ
JPS58101360A (ja) デ−タ処理装置
JP3314948B2 (ja) マルチｃｐｕ構成のプログラマブルコントローラにおけるデータ交換方式
JPS6010343B2 (ja) 情報処理系の制御方式
JPH059815B2 (en:Method)
JPS61150546A (ja) デ−タ伝送制御方式
KR930022207A (ko) 마스터/슬레이브 메모리 공유장치와 공유 제어방법
JPS61103268A (ja) 密結合マルチプロセツサ割込制御方式
JPS61151745A (ja) 割込処理方式
JPH03168860A (ja) 並列プロセッサのバッファ記憶制御装置
KR960007835B1 (ko) 다중 프로세서의 공통 메모리 억세스 장치
JPH0192862A (ja) データ処理装置
JPS6016655B2 (ja) 入出力装置アクセス制御方式
JPS63120303A (ja) 汎用コントロ−ラ
KR19980015549A (ko) 다수 프로세서간의 통신장치
KR910003497A (ko) 내부 버스라인 수를 줄인 데이타 처리장치
JPS62241057A (ja) 入出力処理高速化回路
JPS63197260A (ja) 記憶装置制御方式