JPS6155254B2 - - Google Patents

Info

Publication number
JPS6155254B2
JPS6155254B2 JP55100209A JP10020980A JPS6155254B2 JP S6155254 B2 JPS6155254 B2 JP S6155254B2 JP 55100209 A JP55100209 A JP 55100209A JP 10020980 A JP10020980 A JP 10020980A JP S6155254 B2 JPS6155254 B2 JP S6155254B2
Authority
JP
Japan
Prior art keywords
semiconductor chip
semiconductor device
hermetically sealed
semiconductor
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55100209A
Other languages
English (en)
Other versions
JPS5724554A (en
Inventor
Hiroshi Yokota
Kazuo Okano
Takayuki Uno
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP10020980A priority Critical patent/JPS5724554A/ja
Publication of JPS5724554A publication Critical patent/JPS5724554A/ja
Publication of JPS6155254B2 publication Critical patent/JPS6155254B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H01L23/556—Protection against radiation, e.g. light or electromagnetic waves against alpha rays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Landscapes

  • Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

【発明の詳細な説明】 本発明は、気密封止してなる半導体装置に関
し、特に、半導体チツプ表面を樹脂にて被覆して
なる気密封止型半導体装置に関する。
従来の気密封止型半導体装置は、例えば第１図
に示すように、半導体チツプ５を搭載するダイア
タツチ部を有するアルミナ等から成る半導体チツ
プ甲パツケージ１に、半導体チツプ５を金属ロー
材、樹脂ペースト等で搭載し、半導体チツプの電
極６は、金属細線７を用いて、半導体チツプ用パ
ツケージの外部接続用リード２に接続され、その
後アルミナ、ベリリア等のセラミツクあるいはコ
バール等の蓋部材３を樹脂性接着剤、ガラス性接
着剤、金属ロー材等の接着部材４で封止あるいは
溶接せしめたものである。
あるいは、第２図に示すように、封止時に発生
する半導体チツプに有害なガスから半導体チツプ
１５を保護するため、また気密性が不十分で半導
体チツプ１５を外気から保護する必要がある場合
等に、半導体チツプ上を樹脂１８でおおい半導体
チツプ表面安定化を計つたもの等が考案されてい
る。この場合樹脂の目的は半導体チツプ表面安定
化にあり、樹脂の厚さは、うすくてよかつた。
しかしながらかかる従来の気密封止型半導体装
置において、以下の問題が生じた。特に近年、半
導体チツプ内の素子の集積度の増加がいちじるし
いMOSダイナミツクRAM，ROM、あるいは
CCD等においてその問題は顕著化してきた。
すなわち、半導体用パツケージ材とし使用して
いる。アルミナあるいは蓋部材として使用してい
るアルミナ、ベリリア、コバール等には、ウラ
ン、トリウム等の放射性元素が含まれ、該放射性
元素からは、α粒子が放射されている。よつて前
記パツケージに実装された半導体チツプには、前
記パツケージ材あるいは蓋部材から放射されるα
粒子が照射される。そのため、たとえばMOS
FETの場合ゲート部にα粒子が照射すると、半
導体中に、ホールとエレクトロンの対が出来、こ
のエレクトロンがゲートの下に電荷を生じさせ、
誤動作の原因となる。ゲート部にα粒子が照射す
る確率は、素子の集積度が増加すればするほど高
くなり近年のように、素子の集積度が増加してく
ると、α粒子の照射が無視できなくなつてきた。
本発明の目的は、かかる従来の気密封止型半導
体装置の欠点を除去した新しい気密封止型半導体
装置を提供することにある。
上記目的を達成するために、気密封止型半導体
装置の半導体ペレツト表面をゲルタイプシリコー
ン樹脂でおおい、かつ該樹脂膜を50μｍ（ミクロ
ン）以上形成した。
樹脂膜のα粒子遮蔽効果を、種々の樹脂にて、
調査したところ、ポリイミド樹脂、エポキシ樹
脂、シリコーン樹脂等の樹脂においては、その膜
厚が50ミクロン以上有ると完全にα粒子を遮蔽す
ることが確認できた。
しかしながら本願以外の樹脂は硬化後の膜質は
硬いため、膜厚を厚くする場合あるいは、熱的ス
トレスが加わる場合例えば熱シヨツク温度サイク
ル等の試験後に、膜にクラツクが生じたり、半導
体ペレツト電極と金属細線との接続部でルーズコ
ンタクトによる不良が発生する恐れが生じた。
かかる問題を除去するため本願の請求するとこ
ろは、α粒子遮蔽効果を具備しかつ、膜厚を厚く
する場合あるいは、熱ストレスが加わつた場合に
膜にクラツクが入らず、ルーズコンタクトの発生
の恐れがないゲルタイプシリコーン樹脂を50ミク
ロン以上半導体ペレツト上に形成することにあ
る。
以下に実施例によつて説明する。第３図に、本
願による気密封止型半導体装置を示す。
外部接続用リード２２を有する半導体チツプ用
パツケージ２１のダイアタツチ部に例えば64Kダ
イナミツクMOS RAM半導体チツプ２５を搭載
する。次に半導体チツプの電極２６と外部接続用
リード２２を30ミクロンのアルミニウム細線２７
を用いて、超音波がボンデイングする。次に、ゲ
ルタイプシリコーン樹脂例えば東レシリコーン社
より市販されているJCR−6108を半導体チツプ上
に、ポツテイングし、次に樹脂を硬化するため、
常温30分→100℃30分→200℃30分の熱処理を施こ
し50ミクロン以上のゲルタイプシリコーン樹脂膜
２８を形成する。その後コバールよりなる蓋材２
３をウエルド法により、半導体チツプ用パツケー
ジ２１に溶接封止する。
かかる半導体装置に対し、例えばリテンシヨン
法なるα粒子加速試験を行なつたところ全く不良
が発生することはなかつた。また熱的ストレス試
験例えば熱シヨツク、温度サイクル試験等におい
て樹脂膜のクラツク、および半導体チツプ電極と
金属細線との接続不良いわゆるルーズコンタクト
の発生等は、全く皆無であつた。以上の様に、本
願によれば、α粒子照射に対する十分な遮蔽効果
を有する半導体装置を得ることができる。
【図面の簡単な説明】
第１図は従来の気密封止型半導体装置の断面
図、第２図は従来の改良された気密封止型半導体
装置の断面図、第３図は本願の実施例による気密
封止型半導体装置の断面図を示す。 図において１，１１，２１……半導体チツプ用
パツケージ、２，１２，２２……外部接続用リー
ド、３，１３，２３……蓋材、４，１４……封着
部材、５，１５，２５……半導体チツプ、６，１
６，２６……半導体チツプ電極、７，１７，２７
……金属細線、１８……樹脂膜、２８……ゲルタ
イプシリコーン樹脂膜である。

Claims (1)

    【特許請求の範囲】
  1. １ セラミツクパツケージに半導体チツプを搭載
    し、蓋材を溶接することにより気密封止してなる
    半導体装置において、前記セラミツクパツケージ
    の内側面に達しないように前記半導体チツプの表
    面を50ミクロン以上の膜厚を有するゲルタイプシ
    リコーン樹脂でおおい、これによりパツケージを
    構成するセラミツク材や蓋材からのα線照射から
    前記半導体チツプを遮蔽することを特徴とする半
    導体装置。
JP10020980A 1980-07-22 1980-07-22 Semiconductor device Granted JPS5724554A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10020980A JPS5724554A (en) 1980-07-22 1980-07-22 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10020980A JPS5724554A (en) 1980-07-22 1980-07-22 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS5724554A JPS5724554A (en) 1982-02-09
JPS6155254B2 true JPS6155254B2 (ja) 1986-11-27

Family

ID=14267907

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10020980A Granted JPS5724554A (en) 1980-07-22 1980-07-22 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5724554A (ja)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6038842A (ja) * 1983-08-12 1985-02-28 Hitachi Ltd ピングリッドアレイ型半導体パッケージ
JPS60133741A (ja) * 1983-12-21 1985-07-16 Fujitsu Ltd 半導体装置及びその製造方法
JPH0446259Y2 (ja) * 1984-09-19 1992-10-30
JPS61126285U (ja) * 1985-01-28 1986-08-08

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54122132A (en) * 1978-03-16 1979-09-21 Ricoh Co Ltd Slit exposure method for photreceptor in copier
JPS5567486A (en) * 1978-11-14 1980-05-21 Seiko Epson Corp Thermal printer
JPS5588356A (en) * 1978-12-27 1980-07-04 Hitachi Ltd Semiconductor device
JPS5623759A (en) * 1979-08-01 1981-03-06 Hitachi Ltd Resin-sealed semiconductor device and manufacture thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54122132A (en) * 1978-03-16 1979-09-21 Ricoh Co Ltd Slit exposure method for photreceptor in copier
JPS5567486A (en) * 1978-11-14 1980-05-21 Seiko Epson Corp Thermal printer
JPS5588356A (en) * 1978-12-27 1980-07-04 Hitachi Ltd Semiconductor device
JPS5623759A (en) * 1979-08-01 1981-03-06 Hitachi Ltd Resin-sealed semiconductor device and manufacture thereof

Also Published As

Publication number Publication date
JPS5724554A (en) 1982-02-09

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