JPS6136959A - 樹脂封止型半導体装置 - Google Patents

樹脂封止型半導体装置

Info

Publication number
JPS6136959A
JPS6136959A JP15965084A JP15965084A JPS6136959A JP S6136959 A JPS6136959 A JP S6136959A JP 15965084 A JP15965084 A JP 15965084A JP 15965084 A JP15965084 A JP 15965084A JP S6136959 A JPS6136959 A JP S6136959A
Authority
JP
Japan
Prior art keywords
chip
stage
resin
lead frame
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15965084A
Other languages
English (en)
Inventor
Tadashi Uno
宇野 正
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP15965084A priority Critical patent/JPS6136959A/ja
Publication of JPS6136959A publication Critical patent/JPS6136959A/ja
Pending legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49503Lead-frames or other flat leads characterised by the die pad
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05554Shape in top view being square
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124Aluminium (Al) as principal constituent
    • HELECTRICITY
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、リード・フレームのチップ・ステージ部に個
有形状を有する樹脂封止型半導体装置に関するものであ
る。
従来例の構成とその問題点 近年、樹脂封止型半導体装置は、低価格、大量生産向き
の特長を生かして、多くの半導体デバイスに用いられて
いる。第1図(イ)、(ロ)は従来の樹脂封止型半導体
装置の平面図及びそのA−A’断面図を示すものであり
、1はリードフレームのチップ・ステージ、2はチップ
、3はボンディング争ワイヤ、4は外部リード、5はボ
ンディング・バント、6は合金層、7は封止用樹脂を示
している。
最近のメモリデバイスのように、メモリ4惜が増大化し
、チップ・サイズが細長く大きくなり、ボンディング・
パッドが、第2図のように、チップ12の相対立する二
辺に分割して、同パッド15が多数配列されたメモリチ
ップが出てきた。ところが、このような径大なチップ面
積構成では、メモリチップを樹脂封止する場合、第1図
示のリードフレームで、チップ・ステージ及びチップが
一方向にだけ固定されていると、第2図のy軸を中心と
する回転力が加わり易く、ボンディング・ワイヤの断線
を発生させるなど、組立加工歩留りの低減という問題点
を有していた。
発明の目的 本発明は上記従来の問題点を解消するもので、樹脂封止
加工時のチップ・ステージを回転させる力を緩和させ、
組立加工歩留の低減を防止する新しい形状のチップ・ス
テージを有するリードフレ−ムを用いた樹脂封止型半導
体装置を提供するものである。
発明の構成 本発明は、樹脂封止型半導体装置の構造において、半導
体チップを固定するチップ・ステージのチップの周囲に
1つ又はそれ以上の数の適当な大きさの穴をあけたリー
ドフレームを備えた樹脂封止型半導体装置であり、チッ
プ・ステージにあけた穴の効果により、組立時の加工歩
留りの低減を防止することのできるものである。
実施例の説明 第3図は、本発明の実施例における樹脂封止型半導体装
置を示すものである。第3図において、第2図(イ)、
(ロ)に示す細長い半導体チップを組立てた時の樹脂封
止完成体の平面図及び樹脂モールド後の人−A′断面図
である。
捷ず、本樹脂封止組立加工を行なうには、コバール材等
からなるリードフレームのチップ・ステージ21の側辺
に、穴部28をもっている。そして、このリードフレー
ムは、チップ・ステージ及びワイヤーボンディング領域
等に、例えば金(Au)メッキが施された通常のリード
フレームのチップ・ステージ21上に通常のグイ・ボン
ディング手段によりチップ22をボンディングする。図
中、26ばこのダイボンディング過程で形成されたAu
−3i合金層を示す。
次いで、通常のワイヤ・ボンディング手段により、チッ
プ22のボンディング・バッド26とリード・フレーム
に於けるリード24の内部方向先端部とをAu或いはア
ルミニウム(Ae)細線23で接続する。
次いで上記組立完成体が形成されたリード・フレームを
従来のモールド用金型により、従来と同様エポキシ等の
モールド樹脂を用い150〜180〔°C〕程度の温度
で樹脂成型を行い、次いで150〜18o〔℃〕程度の
温度でモールド樹脂のギ、アーを行って組立完成体を形
成する。
発明の詳細 な説明したように本発明によれば、メモリーデバイス等
の細長い半導体チップを樹脂封止、 7JII Iする
場合、チップ・ステージのチップの1わりにあけた穴の
効果で、樹脂とチップ・ステージの密着性が良く、組立
時の回転力を防止し加工歩留の低減を防止することがで
きる。
【図面の簡単な説明】
第1図(イ)は従来の樹脂封止型半導体装置の樹脂封止
完成体の上面図、同図(ロ)はそのA−A’断面図、第
2図は大容量メモリのチップ図、第3図(イ)は本発明
の実施例における樹脂封止型半導体装置の樹脂封止完成
体の上面図、同図(ロ)はそのA−A’弾絣断面図であ
る。 21・・・・・・チップステージ、22・・・・・・半
導体チップ、23・・・・・・ワイヤ・ボンディング細
線、24・・・・・・金属リード、25・・・・・・ボ
ンディング・バッド、26・・・・・・合金層、27・
・・・・・樹脂、28・・・・・・チップステージの穴
。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
図 rl)2図 !? 7季山 第3図

Claims (1)

    【特許請求の範囲】
  1.  半導体デバイスチップを固定するリード・フレームの
    チップ・ステージを有し、前記チップ・ステージに固定
    されたチップの周囲の前記チップ・ステージに1つ又は
    それ以上の所定形状の穴を設けたことを特徴とする樹脂
    封止型半導体装置。
JP15965084A 1984-07-30 1984-07-30 樹脂封止型半導体装置 Pending JPS6136959A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15965084A JPS6136959A (ja) 1984-07-30 1984-07-30 樹脂封止型半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15965084A JPS6136959A (ja) 1984-07-30 1984-07-30 樹脂封止型半導体装置

Publications (1)

Publication Number Publication Date
JPS6136959A true JPS6136959A (ja) 1986-02-21

Family

ID=15698341

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15965084A Pending JPS6136959A (ja) 1984-07-30 1984-07-30 樹脂封止型半導体装置

Country Status (1)

Country Link
JP (1) JPS6136959A (ja)

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