JPS6125262A - Data transfer device - Google Patents

Abstract

PURPOSE:To shorten a bus cycle by sending immediately the bus answer signal produced from a bus request signal back to an interface part and transmitting the bus request signal to a conflict control circuit after a prescribed period of time. CONSTITUTION:A conflict control circuit 6 performs control to prevent a conflict state of data which are transferred via a data bus 10. An interface part 3 connected to an external device transmits a bus request signal to the circuit 6 and starts the transfer of data with the bus 10 based on the bus answer signal given from the circuit 6. Then the 2nd bus request signal related to the bus request signal is transmitted to the circuit 6. A buffer memory 2 stores the data that pass through the part 3.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to bus control means in a data transfer device.

[Conventional technology]

The conventional data transfer device has the configuration shown in FIG.
In this device, the bus cycle is determined based on the access time of the functional block with the longest access time among the bus access times of each part that accesses the data buffer memory 2, or the bus cycle is handled as an asynchronous signal, and each function A different bus cycle is determined for each block access time.

Here, when the functional block includes a line support unit that takes a long bus access time, and when these make a hash request to the contention control circuit 6, the former hash control method in which the bus cycle is determined is adopted. .

[Problem that the invention seeks to solve]

In a data transfer device that employs such a hash control method, the use of the bus cycle as short as possible, which is desired for upper-level interface and 9 transfers, is hindered, and it is also difficult to use the bus cycle that is desired to improve the hash transfer efficiency. There was a drawback that it was not possible to shorten the cycle time.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate this drawback, and to provide a data transfer device that eliminates bus cycle restrictions imposed by the upper-level interface and can shorten the hash cycle.

[Means for solving problems]

The present invention provides a data bus, a contention control circuit that performs control to avoid a contention state of data transferred via the data bus, and a contention control circuit that is connected to an external device and sends a bus request signal to the contention control circuit. an interface unit that starts an operation related to data exchange with the data bus based on a bus response signal related to the bus request signal from the contention control circuit; a buffer memory that temporarily stores data passing through the interface unit; The above-mentioned problem is solved by a data transfer device having a bus cycle having either a fixed time length equal to the access time of the ink face section to this buffer memory or a shorter fixed time length. As a means for this, the above-mentioned interface member is inserted between the means competition control circuit, and the bus response signal based on the above-mentioned bus request signal is immediately returned to the interface section related to this bus request signal, and after a predetermined period of time, this bus response signal is returned to the interface section related to this bus request signal. The present invention is characterized by comprising means for sending a second bus request signal related to the request signal to the contention control circuit.

[Effect]

When a bus request signal is sent from the interface unit that exchanges data with an external device to the second control unit at the time of starting execution of data transfer, a bus response signal is immediately returned to this interface unit. , this interface section starts operations required for data exchange with the data buffer memory. On the other hand, the second control section applies a second bus request signal to the contention control circuit after receiving the bus request signal.

In this contention control circuit, when a bus cycle due to another bus request ends, the second bus response signal is used as the main signal, and data transfer via the ink face section is controlled by this signal between the data buffer memory and the data buffer memory. executed.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS A device according to an embodiment of the present invention will be explained below based on the drawings. FIG. 1 is a block diagram showing the configuration of the apparatus of this embodiment. FIG. 2 is a block diagram showing in detail extracted parts related to the present invention in this embodiment apparatus. Third
This figure is a waveform diagram showing the timing of signals of each part of the embodiment device shown in FIG. 2.

First, the configuration of this embodiment device will be explained based on FIGS. 1 and 2. This embodiment device includes a control section 1, a data buffer memory 2 having a contention control circuit 6, a host device interface section 3, line correspondence sections 4 and 5, line bus control circuits 7 and 8, and a bus 10. Be prepared. Here, the parts related to the present invention, such as the line correspondence section 4, the line bus control circuit 7 connected thereto, the data buffer memory 6 including the contention control circuit 6, and the control section l related thereto will be explained. This will be explained in more detail based on FIG. In other words, the control section of this part is a direct memory access circuit (
Hereinafter, this will be referred to as a DMA circuit. ) 21 and bus selection circuit 22
．． 23 and 24, and a timing circuit 25, and the bus 10 includes a data bus 51 and an address bus 52.

The data input/output of the line correspondence section 4 is carried out by the first bus selection circuit 22.
The second data input/output of the first bus selection circuit 22 is connected to the first data input/output of the bus selection circuit 23 via the data bus 51. The second data input/output of the bus selection circuit 23 is connected to the data input/output of the data buffer memory 2 so as to exchange data. The second control signal input/output of the line corresponding section 4 is connected to the first control signal input/output of the line bus control circuit 7 to exchange signals, and the second control signal output of the line bus control circuit 7 is connected to the first control signal input/output of the line bus control circuit 7. The third control signal output of the line bus control circuit 7 is connected to the first control signal input of the control circuit 6 and the DMA circuit 21
connected to the control signal input of the The first control body of the contention control circuit 6.

The signal output is connected to a second control signal input of the line bus control circuit 7 and a control signal input of the first bus control circuit 22. The address signal output of the DMA circuit 21 is the address bus 5.
2 to the address signal input of the third bus selection circuit 24, and the address signal output of the third bus selection circuit 24 is connected to the address signal input of the data buffer memory 2. The second output of the contention control circuit 6 is the control signal input of the second bus selection circuit 23 and the third bus selection circuit 24.
A third control signal output of the contention control circuit 6 is connected to a control signal input of the timing circuit 25, and a control signal output of the timing circuit 25 is connected to a control signal input of the data buffer memory 2. Ru.

Next, the operation of this embodiment device will be explained based on FIGS. 2 and 3.

When the line support unit 4 transfers data received from the line to the data buffer memory 2 via the data bus 51,
First, a first bus request signal is output to the line bus control circuit 7. In the line bus control circuit 7, the first bus response signal based on the reception of the first bus request signal is returned to the line corresponding section 4, and after the time of bus cycle C shown in FIG. A request signal is sent to the competition control circuit 6.

In the contention circuit 6, after receiving the second bus request signal and after completing the bus cycle due to another bus request, the second bus response signal is returned to the line bus control circuit 7. At the same time, the timing circuit 2 is brought into operation by the control output of the contention control circuit 6, and the second bus selection circuit 23 and the third bus selection circuit 24 are brought into use. The concave line bus control circuit 7 inputting the second bus response signal is the DAM circuit 2.
1 is put into use, and an address signal is sent to the data buffer memory 2 via the address bus 52. Further, when the preparation of the write data to the data buffer memory 2 in the line corresponding section 4 which has already received the first bus response signal is completed, this write data is already in the used state by the second response signal. The data is written into the data buffer memory 2 via the data bus 51.

Similarly, the data stored in the data buffer memory 2 is transferred to the line corresponding section 4 by a read operation including control using the first bus request signal, the first lotus response signal, the second bus learning signal, and the second bus response signal. be done.

Although the device of this embodiment has two line handling units, the present invention can be practiced with a data transfer device having any number of line handling units.

〔Effect of the invention〕

As explained above, the present invention is a data transfer device that uses a bus control method in which a bus cycle is a fixed time.
Even if the bus cycle is determined based on the bus access time of the upper interface with a short bus access time, control of the line corresponding part with a long bus access time can be executed.
This has the effect of improving transfer efficiency on the bus.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the remaining configuration of the device according to the embodiment of the present invention. FIG. 2 is a block configuration diagram showing the configuration of a portion of an apparatus according to an embodiment of the present invention. FIG. 3 is a timing chart showing the operation of the device according to the embodiment of the present invention. FIG. 4 is a block configuration diagram showing the configuration of a conventional device. DESCRIPTION OF SYMBOLS 1...Control part, 2...Data buffer memory, 3.
... Upper device interface section, 4.5... Line correspondence section, 6... Competition control circuit, 7.8... Line bus control circuit, 10... Bus, 21... DMA circuit, 22 ．．
23.24... Bus selection circuit, 25... Timing circuit, Separate... Data bus, 52... Address bus. Atsushi 2 Figure 713 Loh leather 4 Figure

Claims (1)

[Claims] (1) A data bus, a contention control circuit that performs control to avoid a contention state of data transferred via this data bus, and an external device that sends a bus request signal to this contention control circuit. an interface unit that starts an operation related to data exchange with the data bus based on a bus response signal related to the bus request signal from the contention control circuit; a buffer memory that temporarily stores data passing through the interface unit; A data transfer device comprising: a control means having a bus cycle having either a fixed time length equal to the access time of the interface section to the buffer memory or a shorter fixed time length, the interface section and the contention control means; The bus response signal based on the bus request signal is immediately returned to the interface section related to this bus request signal, and after a predetermined time has elapsed, a second bus request signal related to this bus request signal is sent back to the competing interface section. A data transfer device characterized by comprising means for sending data to a control circuit.