JPH05100994A - Dma transfer operation confirming system - Google Patents

Abstract

PURPOSE:To certainly operate data transfer by way of a bus by a DMA master so as to improve the reliability of a system by permitting the DNA master to certainly gain the using right of the bus even when discrepancy occurs in a bus adjusting circuit. CONSTITUTION:The system is provided with a bus using right gaining means 1 making an optional DMA master gain the using right of the bus by outputting an acknowledging signal acknowledging the optional DMA master to use the bus at a next bus clock cycle when a request signal is inputted from the optional DMA master among plural DMA masters 1, 3 gaining the using right of the bus by outputting the request signal to the bus adjusting circuit 9. The system is also provided with a selecting means making the plural DMA masters 1 and 3 gain the using right by the selection of the bus using right gaining means 11 or the bus adjusting means 9 outputting the acknowledging signal acknowledging to use the bus when the request signal to gain the using right of the bus 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus, a bus arbitration circuit which outputs an acknowledge signal for permitting the use of the bus when a request signal for acquiring the right to use the bus is input, and the bus arbitration circuit. Among the DMA transfer operation confirmation methods that include a plurality of DMA masters that output a request signal to acquire the bus usage right, in particular, the DMA master is made sure to acquire the bus usage right and The present invention relates to a DMA transfer operation confirmation method capable of confirming a transfer operation.

[0002]

2. Description of the Related Art Generally, an external storage device of a computer, such as a magnetic disk device and a communication control device, is considerably slower than an operating speed of an internal memory, so that a waiting time of the internal memory may occur. As a method for preventing the occurrence of the waiting time of the internal memory and executing the data transfer between the external storage device of the computer and the internal memory at high speed, the DMA
There is a (direct memory access) method. Above D
An apparatus that executes the MA method (hereinafter, referred to as a DMA master) executes data transfer to the memory, and thus needs to acquire the right to use the data bus of the memory.

When acquiring the right to use the data bus, the DMA master outputs a request signal to the bus arbitration circuit which manages the right to use the data bus. When the acknowledge signal is input from the bus arbitration circuit in response to the request signal after the request signal is output, the DMA master acquires the right to use the data bus and executes the data transfer, but the bus arbitration circuit has a problem. When it occurred, it was not easy to obtain the right to use the data bus.

[0004]

By the way, conventionally, when a failure occurs in the bus arbitration circuit, an acknowledge signal is not returned from the bus arbitration circuit even if a request signal is output from the DMA master. At the same time, when request signals are input to the bus arbitration circuit from a plurality of DMA masters, the priority order of the input request signals is not determined, so that a defect occurs in the bus arbitration circuit and the acknowledge signal is transmitted to the DMA arbitration circuit. Since it is not output to the master, there is a problem that the DMA master that outputs the request signal cannot acquire the right to use the bus, which causes a delay in the processing of the system.

The present invention has been made in order to solve such a conventional problem, and an object thereof is to reliably obtain a bus mastership right to a DMA master even if a failure occurs in a bus arbitration circuit. By doing so, the data transfer operation by the DMA master is surely executed, and a DMA transfer operation confirmation method for improving system reliability is provided.

[0006]

In order to achieve the above object, the present invention provides a request signal from an arbitrary DMA master among a plurality of DMA masters which outputs a request signal to a bus arbitration circuit and acquires the right to use the bus. Is input, a bus use right acquisition means for outputting an acknowledge signal for permitting use of the bus to the arbitrary DMA master in the next bus clock cycle to acquire the use right of the bus, and this bus use right acquisition means Alternatively, when a request signal for acquiring the right to use the bus is input, selecting means for causing the plurality of DMA masters to acquire the right to use the bus by selecting a bus arbitration circuit that outputs an acknowledge signal to permit the use of the bus. The summary is that

[0007]

According to the above construction, when the selection means selects the acquisition of the bus usage right by the bus usage right acquisition means and a request signal is input from an arbitrary DMA master among a plurality of DMA masters, Since the acknowledge signal for permitting use of the bus is output to the arbitrary DMA master in the bus clock cycle of, the DMA master can surely acquire the right to use the bus even if a failure occurs in the bus arbitration circuit. ..

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the control of an embodiment according to the DMA transfer operation confirmation system of the present invention.

In FIG. 1, DMA master 1 and DM
The A master 3 is connected to the data bus 5 via a data signal line, and receives a bus clock.

The DMA master 1 has a memory 7 which will be described later.
In addition, for example, in order to transfer data from the external storage device of the computer, a request signal (REQ1) indicating a request to acquire the right to use the data bus 5 of the memory 7 is output to the auxiliary circuit 11 described later. Similarly, the DMA master 3 outputs a request signal (REQ2) indicating a request for acquiring the right to use the data bus 5 to the auxiliary circuit 11 described later.

The data bus 5 is, for example, a passage for transferring data from an external storage device of a computer to a memory 7 described later, and is a synchronous bus.

The memory 7 stores the data transferred via the data bus 5 at a predetermined address.

The bus arbitration circuit 9 receives data from the data bus 5 when a request signal (REQ1) is input from the DMA master 1.
Of the acknowledge signal (ACK1X) for permitting the use of the data bus 5 to the auxiliary circuit 11 described later, and when the request signal (REQ2) is input from the DMA master 3, the acknowledge signal (ACK2X) for permitting the use of the data bus 5 is sent to the auxiliary circuit. Output to 11.

The auxiliary circuit 11 is. It is provided between the DMA masters 1 and 3 and the bus arbitration circuit 9, and when a request signal (REQ1 or REQ2) is input from the DMA masters 1 and 3 by ON / OFF control by a CPU 13 described later, an acknowledge signal (ACK1 is forcibly input. Or ACK
2) is output to the DMA masters 1 and 3.

The CPU 13 compulsorily returns an acknowledge signal when a request signal is input from the DMA master 1 and the DMA master 3 when a failure occurs in the bus arbitration circuit 9, so that the ON signal data is written in the register 15. As a result, the ON signal is output to the selector 23 of the auxiliary circuit 11. On the other hand, the CPU 13 uses the bus arbitration circuit 9
If there is no problem in, register OFF
By writing the signal data, the OFF signal is output to the selector 23 of the auxiliary circuit 11. When the request signal is output from the DMA master 1 and the DMA master 3 by the output of the OFF signal, the bus arbitration circuit 9 is switched to the control of returning the acknowledge signal to the DMA masters 1 and 3.

The register 15 includes the AND circuit 17 and the AND circuit 1 together with the selector 23 of the auxiliary circuit 11.
9 connected to ON signal or OF under the control of CPU
Supply the F signal. The AND circuit 17 is a register 1
5 and the DMA master 1 are ANDed, and the register 1
A switch is provided on the 5 side and is masked by the ON signal of the register 15. Further, the AND circuit 19 calculates the logical product of the register 15 and the DMA master 3 and is provided with a switch on the side of the register 15 so that the O
It is masked by the N signal.

The auxiliary circuit 11 described above will be described in detail with reference to FIG.

The auxiliary circuit 11 has a D flip-flop 21 and a selector 23. The D input terminal of the D flip-flop 21 is connected to the AND circuit 17 which takes the logical product of the DMA master 1 and the register 15, and the CLK terminal is connected to the bus clock. The Q output terminal of the D flip-flop 21 is connected to the selector 23, and CL
The Q output terminal goes high in response to the bus clock input from the K terminal. Selector 23 is register 1
5 and the Q output terminal of the D flip-flop 21 and the bus arbitration circuit 9, and when the ON signal is input from the register 15 to input the request signal from the DMA masters 1 and 3, the Q output of the D flip-flop 21 is input. Acknowledge signal (AC
K) is output. On the other hand, when the OFF signal is input from the register 15, the selector 23 sends the acknowledge signal (ACK) from the bus arbitration circuit 9 to the DMA masters 1 and 3 when the request signal (REQ) is input from the DMA masters 1 and 3. return.

Next, the operation of this embodiment will be described.

First, the CPU 13 sets O in the register 15.
When the FF signal is written, the selector 23 of the auxiliary circuit 11
Are switched to the bus arbitration circuit 9 side. At this time, DM
When the request signal (REQ1) is output from the A master 1, it is input to the bus arbitration circuit 9 and also the auxiliary circuit 1
1 is input to the D input terminal of the D flip-flop 21. The bus arbitration circuit 9 uses the request signal (REQ
When 1) is input, an acknowledge signal (ACK1X) that permits use of the bus 5 is output to the selector 23 of the auxiliary circuit 11. Since the selector 23 is switched to the bus arbitration circuit 9 side, it outputs the acknowledge signal (ACK1X) input from the bus arbitration circuit 9 to the DMA master 1. DMA master acknowledge signal (ACK1X)
As a result, the usage right of the bus 5 is acquired and the data transfer is executed via the bus 5.

Next, when a failure occurs in the bus arbitration circuit 9, the CPU 13 writes the data indicating the ON signal in the register 15 so that the selector 23 of the auxiliary circuit 11 outputs D.
Switch to MA master 1 side. The request signal (REQ1) from the DMA master 1 is input to the D input terminal of the D flip-flop 21 of the auxiliary circuit 11 and the bus arbitration circuit 9. The D flip-flop 21
Outputs the Q output terminal to a high level at the Q output terminal in synchronization with the bus clock next to the bus clock input to the CLK terminal. The selector 23 outputs an acknowledge signal (ACK1) to the DMA master 1,
The DMA master 1 acquires the right to use the bus 5 and executes data transfer via the bus 5.

The DMA master 2 operates similarly to the DMA master 1.

Here, even if the request signals are simultaneously output from the DMA master 1 and the DMA master 2, since the request signals are masked when the register is in the ON state, the request signals are simultaneously output. Not even.

As a result, even if a failure occurs in the bus arbitration circuit 9, the acknowledge signal is surely returned to the DMA master, so that the right to use the bus can be surely acquired.
For example, the operation of the DMA during system development can be confirmed.

[0026]

As described above, according to the present invention, when the request signal is input by the auxiliary circuit, the acknowledge signal is returned in the next bus clock cycle. Therefore, even if a failure occurs in the bus arbitration circuit, the DMA By ensuring that the master acquires the right to use the bus, the operation of data transfer through the bus by the DMA master is surely executed,
The system reliability can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing control of an embodiment according to a DMA transfer operation confirmation system of the present invention.

FIG. 2 is a circuit diagram showing an auxiliary circuit.

[Explanation of symbols]

 1,3 DMA master 5 Data bus 7 Memory 9 Bus arbitration circuit 11 Auxiliary circuit 21 D flip-flop 23 Selector

Claims (1)

[Claims] 1. A bus and a license for acquiring the right to use the bus.
Permit use of the bus when a quest signal is input
A bus arbitration circuit that outputs an acknowledge signal and this bus
Acquires the right to use the bus by outputting a request signal to the arbitration circuit
A DMA transfer operation confirmation method comprising: a plurality of DMA masters to be obtained;
When the request signal is input, the next bus clock cycle
To allow any DMA master to use the bus.
Acknowledge signal is output to acquire the right to use the bus
Bus usage right acquisition means for selecting the bus usage right acquisition means or the bus arbitration circuit
To acquire the right to use the bus to the plurality of DMA masters.
A DMA transfer operation confirmation method comprising: a selection unit for obtaining the DMA transfer operation.