JPH08241272A - Bus interface device - Google Patents

Abstract

PURPOSE: To unnecessitate the dead cycle for evading a bus fight and to improve the utilizing efficiency of an input/output device and an input/output bus. CONSTITUTION: An address to be outputted from a processor 100 to an input/ output device 400 is temporarily transferred to a write address buffer 330 from an input/output bus address buffer 260 via an input/output bus 410. When the input/output bus 410 is occupied at the time of this transfer, the transfer is performed by using an address transfer bus 269. An address data input/output selector 340 successively outputs the data held in an input/output bus data buffer 320 or the address held in the write address buffer 330 to the input/output bus 410.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus interface device for interfacing between a system bus and an input / output bus, and more particularly to efficiently write transactions from a processor on the system bus to an input / output device on the input / output bus. The present invention relates to a bus interface device for performing the operation.

[0002]

2. Description of the Related Art A bus interface device for connecting a system bus and an input / output bus may be mounted by being divided into a plurality of mounting units such as an address system and a data system depending on mounting requirements. That is, there are restrictions on the area and the number of input / output pins for mounting units such as boards and LSIs, and if these are not satisfied, it is necessary to divide the mounting units. The mounting units thus divided are normally synchronized with each other, but a slight deviation may occur due to clock skew or the like. Therefore, data from a plurality of mounting units may collide on the bus. Such collision of the data sent from the drivers on a plurality of mounting units on the bus is called a bus fight. When this bus fight occurs, the driver that sends data onto the bus may be destroyed. On the other hand, in the conventional technique, this bus fight is avoided by waiting for a certain period (hereinafter referred to as "dead cycle") of data transmission.

Referring to FIG. 7, in the prior art,
When the I / O bus is a bus for both address and data,
By providing a dead cycle (A2) between the sending of the address (A1) and the sending of the data (A3) onto the bus, the write transaction is executed to the input / output device while avoiding the bus fight. There is. When the I / O device cannot receive the write transaction, a retry response is sent to that effect (B1), and the address is again sent to the I / O bus (A1).
4), dead cycle (A5), and data transmission (A6).

Further, Japanese Patent Publication No. 4-61387 discloses that
There is described a technique for reducing the dead cycle to half of one cycle to speed up data transfer. In this technique, the dead cycle is reduced by transmitting the output permission timing after 1/2 cycle of the bus use permission signal by the data transmission period creating means.

[0005]

When the above-mentioned conventional technique is used, a dead cycle must be provided in order to avoid a bus fight when outputting to an address / data dual-purpose bus, and the I / O device There is a problem that the occupied time increases and the data processing time of the input / output device increases. Further, since a dead cycle is provided also during the retry response, there is a problem that the input / output device is occupied for a long time, the input / output bus is occupied for a long period, and the load on the input / output bus is increased.

Further, in the technique described in the above publication, although the dead cycle is shortened, there is a problem that the dead cycle is still required and it is not a fundamental solution.

An object of the present invention is to solve the above-mentioned problems, eliminate the need for a dead cycle for avoiding a bus fight, and improve the use efficiency of an input / output device.

Another object of the present invention is to improve the use efficiency of the input / output device and the input / output bus at the time of retry response.

Another object of the present invention is to improve the transfer throughput by preparing in advance the next use of the input / output bus even when the input / output bus is in use.

[0010]

In order to solve the above-mentioned problems, a bus interface device of the present invention comprises a first bus for connecting a first processing device for instructing writing, and writing by the first processing device. In a bus interface device that mediates a second bus connecting a second processing device, the first interface means that mediates a part of information on the first bus, and the first interface means. Second interface means for mediating information of the remaining part of the information on the bus, and a transfer path connecting between the first interface means and the second interface means, The first interface means transfers the part of the information to the second interface means via one of the second bus and the transfer path, and the second interface means transfers the partial information to the second interface. Scan means outputs the first said part of the information received from the interface means and its remaining information sequentially to the second bus.

In another bus interface device of the present invention, a first bus connecting a first processing device for designating writing by designating an address and data and a writing instruction by the first processing device. A bus interface device that mediates an address connecting the second processing device and a second bus that also serves as data, and an address interface means that mediates an address from the first bus; Data interface means for mediating the data of the above, and address transfer means for transferring an address from the address interface means to the data interface means, wherein the address interface means holds a first address from the first processing device. Address holding circuit and the address held in this first address holding circuit A bus control circuit for controlling transfer to the data interface means and controlling output of an address and data from the data interface means to the second bus, wherein the data interface means includes data from the first processing device. A data holding circuit for holding the address, a second address holding circuit for holding an address from the address interface means, an address held in the second address holding circuit and data held in the data holding circuit in sequence. A selector for outputting to a second bus, and when the first processing device issues a write instruction to the second processing device, the bus control circuit causes the first address holding circuit to perform the write operation. The address is added to the second address holding circuit via either the second bus or the address transfer means. To transfer a scan.

In another bus interface device of the present invention, a first bus connecting a first processing device for designating writing by designating an address and data and a writing instruction by the first processing device. A bus interface device that mediates an address connecting the second processing device and a second bus that also serves as data, and an address interface means that mediates an address from the first bus; Data interface means for mediating the data of, the address interface means,
A first address holding circuit that holds an address from the first processing device, and a transfer of the address held in the first address holding circuit to the data interface unit are controlled to control the data interface unit from the data interface unit. A bus control circuit for controlling output of an address and data to the second bus; the data interface means holds a data holding circuit for holding data from the first processing device; and an address from the address interface means. And a selector for sequentially outputting the address held in the second address holding circuit and the data held in the data holding circuit to the second bus. Address transfer for transferring an address from the second address holding circuit to the second address holding circuit Further comprising a stage, and when writing is instructed from the first processing device to the second processing device, if the second bus is not blocked, then the second bus is used, If the second bus is blocked, the address is transferred via the address transfer means.

Further, in another bus interface device of the present invention, the address transfer means has a transfer width narrower than that of the second bus, and the address interface means is held in the first address holding means. The data interface means further includes means for returning the divided address transferred by the address transfer means to a state before the division.

In another bus interface device of the present invention, when the bus control circuit receives a retry response from the second processing device, the address and the data held in the second address holding circuit. The data held in the holding circuit is controlled to be sequentially output to the second processing device via the second bus.

Further, in another bus interface device of the present invention, the bus control circuit receives the retry response from the second processing device, and the address and the data held in the second address holding circuit. The data held in the holding circuit is controlled to be sequentially output to the second processing device via the second bus.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a first embodiment of the bus interface device of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, a bus interface device according to an embodiment of the present invention connects a system bus 110 and an input / output bus 410. The system bus 110 (hereinafter, also referred to as S bus) is a split bus including an address / control signal bus 111 and a data bus 112, and is connected to the processor 100.
An input / output bus 410 (hereinafter, also referred to as an IO bus) is a multiplexer bus for both address and data, and an input / output device 400 is connected to it.

The SBus interface controller 220 is
From the S bus address command buffer 210 to the signal line 21
Check the S bus address and command input by 1. As a result, if the command is a write transaction, the S bus address command buffer 210,
Address transfer cycle indicator 230, DMA transfer counter 290, data bus interface device 300
To the S bus data buffer 310 of each of the signal lines 21
1, 225, 226, and data acquisition notification line 22
Notify by 9.

IO bus interface controller 270
Is the address transfer cycle indicator 2 through the signal line 232.
30 and instructions from the DMA transfer counter 290 via the signal line 296 and instructions from the address output cycle indicator 240 via the signal line 245. As a result, the notification to the IO bus address buffer 260 by the signal line 271 and the address transfer cycle notification line 274 are given.
And the address output cycle notification line 273 to notify the address / data input / output selector 340 of the data system bus interface device 300, and the data system bus interface device 3 via the address division transfer cycle notification line 275.
00 is sent to the write address selector 350.

The DMA transfer counter 290 is a counter which sets the transfer length of the burst DMA transaction from the input / output device 400 as an initial value and decrements the value each time the transfer in clock units is completed thereafter.

The address transfer path 269 is used for the IO bus 41.
The bit width of 0 is divided into four. As a result, the address bus interface device 200 transfers the write address divided into four to the data bus interface device 300 via the address transfer path 269. The address division circuit 265 divides this address.

When the IO bus interface control unit 270 notifies the retry response control unit 250 of the retry response from the input / output device 400 through the signal line 272, the retry response control unit 250 informs the address output cycle indicator 240 through the signal line 255. Notify that. Here, the retry response is a response indicating that the input / output device 400 is busy and cannot receive the requested transaction.

Address / data input / output selector 340
Responds to instructions from the address transfer cycle notification line 274 and the address output cycle notification line 273, in response to the write address buffer 330 or the IO data buffer 32.
The value held at 0 is selected and output to the IO bus 410.

The write address selector 350, in response to an instruction from the address division transfer notification line 275, sequentially transfers the four divided addresses from the address transfer path 269 to the write address buffer 330.

Next, the operation of the present invention will be described with reference to FIGS.

From the processor 100 onto the S bus 110,
When the address, the command, and the data are output, the address bus interface device 200 operates on the signal line 201.
The above address and command are held in the S bus address command buffer 210. In addition, the data bus interface device 300 holds the data from the signal line 301 in the S bus data buffer 310.

The S bus interface control unit 220 uses the S
The address and command held in the bus address command buffer 210 are monitored by the signal line 211, and when it is determined that the request of the SBus 110 is a write transaction to the input / output device 400, the signal line 226 causes the DMA transfer counter 290 Read count value (J
1). At this time, the S bus address command buffer 210 is instructed to transfer to the IO bus address buffer 260 using the signal line 211.

S bus address command buffer 210
Transfers the address held by the instruction from the S bus interface control unit 220 to the IO bus address buffer 260 via the signal line 212, and holds the address in the IO bus address buffer 260.

Further, the SBus interface control unit 220
Uses the data fetch notification line 229 to indicate that the data fetch cycle is the data bus interface device 3
Tell 00.

When the S bus data buffer 310 of the data bus interface unit 300 receives a data fetch cycle instruction from the data fetch notification line 229, it uses the signal line 315 to make the IO bus data buffer 32.
The data is transferred to 0, and the IO bus data buffer 320 holds the data.

Next, when issuing a write transaction to the input / output device 400, the count value (J1) of the DMA transfer counter 290 read from the signal line 226 to the system bus interface controller 220 is 2 or less. The operation in the case (step 601) will be described with reference to FIGS. 1 to 3 and 6.

The address transfer cycle indicator 230 checks the value of the DMA transfer counter 290 when it is notified by the signal line 225 that the write transaction is from the SBus interface control unit 220 to the input / output device 400. The value of this DMA transfer counter 290 is 0
If it is larger than 0, wait until it becomes 0 or less (step 60).
2). If the value of the DMA transfer counter 290 is 0 or less, the signal transfer line 232 asserts the address transfer cycle notification line 274 via the IO bus interface control unit 270 (step 603).

The IO bus interface control unit 270 is
The address transfer cycle notification line 274 is asserted, and at the same time, the signal is transmitted to the IO bus address buffer 260 via the signal 271 to output the address to the IO bus 410.

The IO bus address buffer 260 outputs an address to the IO bus 410 according to an instruction from the signal line 271 (L1, step 604).

In the data bus interface device 300, when the address / data input / output selector 340 recognizes the address transfer cycle by the instruction of the address transfer cycle notification line 273, the address is input from the IO bus 410 and the signal line 335 is input. Is stored in the write address buffer 330 (step 605).

When the address output cycle indicator 240 is informed of the address transfer cycle by the signal 231 from the address transfer cycle indicator 230, the address output cycle indicator 240 notifies the IO bus interface control unit 270 by the signal 245 to notify the IO bus interface. The address output cycle notification line 273 is asserted via the control unit 270 (M1, step 606).

When the data-system bus interface device 300 is notified of the address output cycle, the address / data input / output selector 340 first selects the address held in the write address buffer 330 and outputs it to the IO bus 410. Output (L2, step 60
7) After that, the data held in the IO bus data buffer 320 is selected and output to the IO bus 410 (L3,
Step 608). As a result, a write transaction to the input / output device 400 is executed.

When the retry response control unit 250 receives the retry response from the input / output device 400 via the IO bus interface control unit 270 (step 609), the address output cycle indicator 240 is notified by using the signal line 255. Tell. Address output cycle indicator 230
Asserts the address output cycle notification line 273 via the signal line 245 via the IO bus interface control unit 270 to notify the data bus interface device 300 of the address output cycle (M2, step 606).

In the data bus interface unit 300, the address / data input / output selector 340 selects the address held in the write address buffer 330 when receiving the address output cycle notification in accordance with the instruction from the address output cycle notification line 273. IO bus 4
10 (L5, step 607) and subsequently the data held in the IO bus data buffer 320 is transferred to the signal line 32.
5 to the IO bus 410 (L6, step 608). As a result, from the address bus interface device 200 to the data bus interface device 300.
The address transfer cycle to the I / O device 40 is omitted.
A write transaction to 0 is executed.

Next, when the write transaction is issued to the input / output device 400, the count value (J1) of the DMA transfer counter 290 read from the signal line 226 to the system bus interface controller 220 is 3 or more. The operation in the case (step 601) will be described with reference to FIGS. 1 and 4 to 6.

The DMA transfer counter 290 is connected to the signal line 22.
When the write transaction from the SBus interface control unit 220 to the I / O device 400 is transmitted by the command line 6, the address division transfer cycle notification line 275 is asserted via the IO bus interface control unit 270 by the signal line 296 (step 611).

The IO bus interface control unit 270 is
The address division transfer cycle notification line 275 is asserted, and at the same time, the signal line 271 is transmitted to the IO bus address buffer 260 so as to sequentially output the divided addresses to the address transfer path 269.

The IO bus address buffer 260 sequentially outputs addresses to the address transfer path 269 according to an instruction from the signal line 271 (step 612). On this occasion,
The address division circuit 265 divides the address into four.

In the data-system bus interface device 300, when the write address selector 350 recognizes the address division transfer cycle by the instruction of the address division transfer cycle notification line 275, the address transfer path 2
Addresses are sequentially received from 69 and held in the write address buffer 330 by the signal line 355 (step 613).

The address output cycle indicator 240 has a D
The count value of the MA transfer counter 290 is monitored by the signal line 295. When the count value becomes 1 or less (J2, step 614), the signal line 245 notifies the IO bus interface control unit 270. In response to this, the IO bus interface control unit 270 asserts the address output cycle notification line 273 (step 6).
06).

In the data bus interface device 300, when the address / data input / output selector 340 recognizes the address output cycle according to the instruction from the address output cycle notification line 273, it selects the address held in the write address buffer 330. And outputs it to the IO bus 410 (L5, step 607), and subsequently selects the data held in the IO bus data buffer 320 and outputs it to the IO bus 410 (L6, step 60).
8). As a result, a write transaction to the input / output device 400 is executed.

When the IO bus interface control unit 270 notifies the retry response control unit 250 that there is a retry response from the input / output device 400, the count value of the DMA transfer counter 290 is 2 or less. Similar to the operation in a certain case, from the address bus interface device 200 to the data bus interface device 300.
The write transaction to the I / O device 400 is executed by omitting the address division transfer cycle to the I / O device 400.

In the present embodiment, the number of divisions of the address has been described as four, but it goes without saying that the division number can take an arbitrary value according to the request of the system.

As described above, according to the bus interface device of the first embodiment of the present invention, the address to the input / output device 400 is addressed to the address bus interface device 200.
From the data system bus interface device 300 to the data system bus interface device 300, addresses and data can be continuously output from the data system bus interface device 300 to avoid a dead cycle. Thereby, the input / output device 400 can be used efficiently. Further, since the address transfer from the address bus interface device 200 to the data bus interface device 300 can be performed by the address transfer path 269, even if the input / output bus 410 is in use, the address is previously set to the data bus interface. It can be transferred to the device 300 in advance, and the throughput of address transfer can be increased.

[0050]

As is apparent from the above description, according to the present invention, the address to the input / output device is temporarily transferred to the data bus interface device, so that the error occurs between the address and the data. It is possible to avoid the dead cycle and improve the usage efficiency of the input / output device.

In the retry process, the address transferred before the retry is used again, so that the address transfer to the data bus interface device does not need to be performed again, and the efficiency of the input / output bus is improved. Can be made.

Further, by providing the dedicated path for address transfer, the address can be transferred to the data bus interface device in advance even when the input / output bus is in use, and the throughput of the address transfer can be increased.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a bus interface device of the present invention.

FIG. 2 is a time chart showing an operation when the DMA counter value of the bus interface device according to the embodiment of the present invention is 2 or less.

FIG. 3 is a time chart showing the details of the operation when the DMA counter value of the bus interface device of one embodiment of the present invention is 2 or less.

FIG. 4 is a time chart showing an operation when the DMA counter value of the bus interface device according to the exemplary embodiment of the present invention is 3 or more.

FIG. 5 is a time chart showing the details of the operation when the DMA counter value of the bus interface device of one embodiment of the present invention is 3 or more.

FIG. 6 is a flowchart showing an operation flow of the bus interface device according to the embodiment of the present invention.

FIG. 7 is a time chart showing an operation of a bus interface device according to a conventional technique.

[Explanation of symbols]

 100 processor 110 system bus 200 address bus interface device 210 system bus address command buffer 220 system bus interface controller 230 address transfer cycle indicator 240 address output cycle indicator 250 retry response controller 260 input / output bus address buffer 265 address division circuit 269 Address Transfer Path 270 Input / Output Bus Interface Control Unit 280 DMA Address Buffer 290 DMA Transfer Counter 300 Data Bus Interface Device 310 System Bus Data Buffer 320 Input / Output Bus Data Buffer 330 Write Address Buffer 340 Address Data Input / Output Selector 350 Write Address Selector 360 DMA data buffer 400 I / O device 4 0 input and output bus

Claims (6)

[Claims] 1. An intermediary between a first bus connecting a first processing unit for instructing writing and a second bus connecting a second processing unit for instructing writing by the first processing unit. In the bus interface device, a first interface means for mediating a part of the information on the first bus, and a second interface for mediating a remaining information of the part of the information on the first bus. Interface means, and a transfer path connecting between the first interface means and the second interface means, the first interface means, the part of the information to the second bus and Transfer to the second interface means via any one of the transfer paths, the second interface means, and the partial information received from the first interface means Bus interface unit and outputs the rest of the information sequentially to the second bus. 2. A first bus for connecting a first processing device for designating writing by designating an address and data and a second processing device for which writing is designated by the first processing device. In a bus interface device that mediates between an address and a second bus that also serves as data, an address interface device that mediates an address from the first bus, and a data interface device that mediates data from the first bus, Address transfer means for transferring an address from the address interface means to the data interface means, wherein the address interface means includes a first address holding circuit for holding an address from the first processing device; Control transfer of address held in address holding circuit to the data interface means A bus control circuit that controls the output of an address and data from the data interface unit to the second bus; the data interface unit includes a data holding circuit that holds data from the first processing device; A second address holding circuit that holds an address from the interface means, and a selector that sequentially outputs the address held in the second address holding circuit and the data held in the data holding circuit to the second bus. And a write instruction from the first processing device to the second processing device, the bus control circuit causes the second address holding circuit to transfer the second address holding circuit from the first address holding circuit to the second address holding circuit. A bus interface for transferring an address through either one of the second bus and the address transfer means. Esu apparatus. 3. A first bus for connecting a first processing device for designating writing by designating an address and data and a second processing device for which writing is designated by the first processing device. In a bus interface device that mediates between an address and a second bus that also serves as data, an address interface device that mediates an address from the first bus and a data interface device that mediates data from the first bus. The address interface means controls a first address holding circuit that holds an address from the first processing device, and a transfer of the address held in the first address holding circuit to the data interface means. Bus control for controlling output of address and data from the data interface means to the second bus A data holding circuit for holding data from the first processing unit, a second address holding circuit for holding an address from the address interface unit, and the second address. A selector for sequentially outputting the address held in the holding circuit and the data held in the data holding circuit to the second bus, wherein the first address holding circuit addresses the second address holding circuit. Address transfer means for transferring the second bus, and when the first processor issues a write command to the second processor, the second bus is not blocked if the second bus is not blocked. Bus-in, characterized in that, if the second bus is blocked, the address is transferred through the address transfer means via the bus. Face equipment. 4. The address transfer means has a transfer width narrower than that of the second bus, and the address interface means further has means for dividing the address held in the first address holding means. However, the data interface means further includes means for returning the divided addresses transferred by the address transfer means to the state before the division.
Bus interface device as described. 5. When the bus control circuit receives a retry response from the second processing device, the bus control circuit sequentially outputs the address held in the second address holding circuit and the data held in the data holding circuit. 4. The bus interface device according to claim 2, wherein the bus interface device is controlled to output to the second processing device via a second bus. 6. When the bus control circuit receives a retry response from the second processing device, the bus control circuit sequentially outputs the address held in the second address holding circuit and the data held in the data holding circuit. 5. The bus interface device according to claim 4, wherein the bus interface device is controlled to output to the second processing device via a second bus.