JP3207329B2 - Bus controller and bus transfer method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus controller for controlling data transfer using a system bus in an information processing apparatus to which a plurality of boards are connected via a system bus.

[0002]

2. Description of the Related Art Today's information processing apparatuses have a CPU (Centra
l Processing Unit) In many cases, a system configuration in which a plurality of boards such as boards are connected by a system bus is used. In an information processing device configured using a system bus, the configuration of the system can be changed on a board basis, and a plurality of boards having different functions are combined to flexibly construct or expand the system. It is possible. In particular, if a plurality of CPU boards are connected by a system bus, a multiprocessor system capable of performing parallel processing can be realized.

FIG. 8 is a block diagram of a general information processing apparatus. 8 includes a CPU board 1, a memory board 2, and an IO connected via a system bus 4.
(Input / Output) It is composed of a plurality of boards such as the board 3. Each of these boards transfers data to other boards via the system bus 4.

FIG. 9 is a block diagram showing an internal configuration of a general CPU board. CPU board 1 is CPU1
1. Program memory 12, data memory 13, bus controller 14, and internal bus 15 connecting them
Consists of The CPU 11 has a program memory 12
And reads data according to the command, or performs an operation on the read data, and outputs the result of the operation. At this time, the CPU 11 reads out data from the data memory 13 in the CPU board 1 or transmits data to the system bus 4 via the bus controller 14.
Or read from. Data is stored in the data memory 1
3 or transmitted to the system bus 4 via the bus controller 14.

In a multiprocessor system, while a certain CPU board 1 is performing data input / output with the system bus 4, the system bus 4 is occupied by the CPU board 1. Cannot use the system bus 4. Therefore, it is important for the bus controller 14 to efficiently control data input / output.

As an apparatus for transferring data on a system bus of such an information processing apparatus, a bus controller (Japanese Patent Application No. Hei 6-26422) using a message transfer method is disclosed.
3, filed on October 27, 1994).

FIG. 10 is a configuration diagram of a CPU board having the bus controller of the prior application. The CPU board 21 shown in FIG.
2, a data memory 25 having a message buffer and a bus controller 27 are provided. CPU board 21
Are connected to other CPU boards, memory boards, IO boards, and the like (not shown) by a system bus 24 to form a multiprocessor system.

The bus controller 27 includes a CPU control unit 2
8, a physical protocol control unit 29, a memory control unit 38, a transmission buffer 31, a reception buffer 39, a message control unit 32, and a DMA control unit 35.

The physical protocol control unit 29 has its own board ID register 30 for storing a board identifier (board ID) of the CPU board 21, and the DMA control unit 35 has an address register 36 for holding an address of the data memory 25. , A data length register 37 for holding the data length of data exchanged with the data memory 25.
The address register 36 and the data length register 37 are provided with two sets, one for writing to the data memory 25 and the other for reading from the data memory 25.

The message control unit 32 has a vector register 34 and a group number register 33, and performs protocol control such as generation and analysis of a message. The vector register 34 holds the head address of the group address table 26 stored in the data memory 25, and the group number register 33 stores the head address of the group address table 26.
Holds the group number as an offset when accessing.

The data memory 25 stores a group address table 26 having a group address 0, a group address 1, and a group address 2, and a plurality of groups of board commands corresponding to each group address. A plurality of board commands of each group are stored as a set together with a board ID and a buffer command address, and a set of a plurality of buffer commands, buffer addresses, and data lengths is stored corresponding to each buffer command address. FIG. 10 shows, as an example, a board command of the group corresponding to the group address 0 and the like.

FIG. 11 shows an example of the structure of data stored in the vector register 34 and the data memory 25 and the relationship between them. The vector register 34 stores, for example, 0
The head address of the group address table 26 represented by 32 bits of to 31 is stored. The group address table 26 stores, for example, addresses of a plurality of board commands represented by 32 bits as a group address.

The message control unit 32 accesses the group address table 26 using the address stored in the vector register 34 as a start address and the value of the group number stored in the group number register 33 as an offset. For example, when the group number is 0, the address of the board command 0-0 is extracted, when the group number is n, the address of the board command n-0 is extracted, and when the group number is m, the address of the board command m-0 is extracted. Take out.

Following the board command n-0 indicated by the address of the board command n-0, the board ID n-
0, address of buffer command n-0-0, board command n-1, board ID n-1, buffer command n
-1-0 address and the like are stored. The board command m indicated by the address of the board command m-0
Following −0, board ID m−0, buffer command m
−0-0 address, board command m−1, board I
Dm-1, the address of the buffer command m-1-0, and the like are stored. Similar storage structures are prepared for other groups. The addresses of these board commands, board IDs, and buffer commands are represented by, for example, 32 bits.

Following the buffer command n-0-0 indicated by the address of the buffer command n-0-0, the address of the buffer n-0-0, the data length of the buffer n-0-0, and the buffer command n-0 0-1, buffer n-0
-1 and the data length of the buffer n-0-1 are stored. Also, following the buffer command n-1-0 indicated by the address of the buffer command n-1-0, the address of the buffer n-1-0, the buffer n-1-0
A data length of 0, a buffer command n-1-1, an address of the buffer n-1-1, a data length of the buffer n-1-1, and the like are stored. The same applies to the storage structure of other buffer commands and the like. These buffer command, buffer address, and buffer data length are also represented by, for example, 32 bits.

The address of buffer n-0-0 points to message buffer n-0-0, and the address of buffer n-0-1 points to message buffer n-0-1. The same applies to the addresses of other buffers. These message buffers have a size of, for example, 32 bits.

FIG. 12 shows an example of a board command. The board command of FIG. 12 is represented using two bits of 0 and 1 among the prepared 32 bits.
If these two bits are 00, it indicates an end command and 0
1 indicates an invalid command, 10 indicates a write command, and 11 indicates a read command.

FIG. 13 shows an example of the buffer command. The buffer command shown in FIG.
For example, it is represented using two bits of 0 and 1 among the bits. If these two bits are 00, they represent an end command, 01 represents an invalid command, and 10 represent a transfer command.

When the CPU board 21 requests data transfer with another board, the CPU control unit 28
When receiving the message transfer request from U22, the message control unit 32 selects one from a plurality of group addresses using the values held in the group number register 33 and the vector register 34. Then, the board command and the buffer command sequentially obtained from the selected group address are analyzed, and the message transfer is controlled.

If the board command is an end command, the transfer is terminated. If the board command is invalid, the transfer to the next board command is skipped. If it is a write command, a write request message is generated on the transmission buffer 31 with the board ID stored following the board command as a transfer destination. If it is a read command, a read request message is generated on the transmission buffer 31 with the board ID stored following the board command as a transfer destination.

The physical protocol control unit 29 converts the request message generated by the message control unit 32 into a transfer protocol specific to the system bus 24 and sends it out, and performs data transfer with the transfer destination board. When the transfer is completed, the physical protocol control unit 29 notifies the CPU control unit 28 of the completion of the transfer.

The message controller 32 analyzes the next board command if the buffer command is an end command, and skips to the next buffer command if the buffer command is invalid. If it is a transfer command, the buffer address and the data length stored following the buffer command are set in the DMA control unit 35.

The DMA controller 35 reads data from the message buffer in the data memory 25 and stores it in the transmission buffer 31 in the case of a write transfer, and stores the data received in the reception buffer 39 in the data memory 25 in the case of a read transfer. In the message buffer. The data stored in the transmission buffer 31 is sent by the physical protocol control unit 29 to the transfer destination board.

When the CPU board 21 responds to data transfer with another board, the bus controller 27 sends the board ID of the transmission destination of the signal transmitted on the system bus 24 to its own board ID register. Compare with the board ID stored in 30. If they match, the physical protocol control unit 29 stores the received message in the reception buffer 39.

The message control unit 32 selects one from a plurality of group addresses using the group number added to the received write request message or read request message and the value held by the vector register 34. Then, the board command and the buffer command sequentially obtained from the selected group address are analyzed, and the message transfer is controlled.

If the board command is an end command, the transfer is terminated. If the board command is invalid, the transfer to the next board command is skipped. If it is a write command or a read command, the corresponding buffer command is analyzed.
If the buffer command is an end command, the next board command is analyzed. If the command is invalid, the process skips to the next buffer command. If it is a transfer command, the buffer address and the data length stored following the buffer command are set in the DMA control unit 35.

If the received message is a write request message, a write permission message to be sent to the request board is generated on the transmission buffer 31. The DMA control unit 35 stores the data received in the reception buffer 39 in the message buffer in the data memory 25 when responding to the write request, and reads the data from the message buffer in the data memory 25 when responding to the read request. And store it in the transmission buffer 31. Transmission buffer 3
The write permission message and data stored in 1 are sent by the physical protocol control unit 29 to the request board.

As described above, the CPU board 21 shown in FIG.
In the above, the CPU 22 groups the board commands of a plurality of boards in advance and prepares them in the data memory 25, so that the identifier of the board of the specific group and the message buffer to be used are automatically set only by specifying the group number. The information is transmitted to the bus controller 27.
As a result, the bus controller 27 transfers a message to a plurality of designated response boards.

[0029]

However, the above-mentioned transfer method using the bus controller has the following problems. In this method, both the request board requesting the transfer and the response board responding to the request operate using the group number specified by the group number register 33 of the request board. That is, a group address corresponding to the group number is obtained, a board command and a buffer command indicated by the group address are analyzed, and a corresponding message buffer is used.

In this case, it is necessary to determine the group numbers to be used so as not to overlap with each other in all boards that perform message transfer. For example, two different
It is assumed that two request boards 1 and 2 perform different message transfers to the same one response board.

First, the group numbers of the response boards are continuously prepared from 0 to 9, and the group addresses 0 to 9 are sequentially arranged in the group address table 26 corresponding to these. Of these, the request board 1 performs transfer using the group numbers 0 to 4, and the request board 2 performs transfer using the group numbers 5 to 9.

At this time, the values of the group numbers 5 to 9 are not used in the request board 1, and the values of the group numbers 0 to 4 are not used in the request board 2. That is, among commands such as a board command and a buffer command arranged in the data memory 25 and other data, some are not used, and the use efficiency of the data memory 25 deteriorates.

The same applies to the case where one request board performs separate message transfer to two response boards 1 and 2 belonging to different groups. In this case, if the group number of the response board 1 is set to 0 and the group number of the response board 2 is set to 1, no value other than the group number 0 is used in the response board 1 and the response board 2
In, values other than the group number 1 are not used. Therefore, a portion not used in the command structure arranged in the data memory 25 occurs, and the use efficiency of the data memory 25 is reduced.

An object of the present invention is to provide a bus controller and a bus transfer method for efficiently transferring data and improving memory use efficiency in an information processing apparatus to which a plurality of boards are connected via a system bus. And

[0035]

SUMMARY OF THE INVENTION The present invention relates to a bus in an information processing apparatus which accesses a memory by a DMA method, processes data stored in the memory, and performs bus transfer by message passing through a system bus. Controller and bus transfer method.

FIG. 1 is a diagram illustrating the principle of a bus controller according to the present invention. The bus controller shown in FIG. 1 includes a physical protocol control unit 52 and a transmission buffer 5 as main components.
3, a reception buffer 54, a message control means 55, and a command pointer control means 56.

The physical protocol control means 52 is connected to the system bus 51 and controls the protocol of a transmission message transmitted on the system bus 51 and a reception message received from the system bus 51.

Transmission buffer 53 and reception buffer 54
Are connected to the physical protocol control means 52, and store the transmitted message and the received message, respectively. The message control means 55 stores information for designating its own command pointer pointing to its own command structure, and transmits the transmission message including the transfer destination identifier of the message with reference to the own command structure. Generated on the buffer 53.

The command pointer control means 56 adds information for designating the command pointer of the transfer destination pointing to the command structure of the transfer destination to the transmission message.

The bus controller of FIG. 1 further includes a DMA control unit 57 and a transfer destination command pointer identifier storage unit 58 as other components. DMA control means 57
Is controlled by the message control means 55, retrieves data from the memory by the DMA method, transfers the data to the transmission buffer 53, and stores data transferred from the reception buffer 54 in the memory by the DMA method.

Destination command pointer identifier storage means 5
Reference numeral 8 stores a transfer destination command pointer identifier used to specify a storage area of the transfer destination command pointer in the transfer destination as information for specifying the transfer destination command pointer. Then, the command pointer control means 56 adds the transfer destination command pointer identifier stored in the transfer destination command pointer identifier storage means 58 to the transmission message.

The information for designating the own command pointer is, for example, the command pointer number of the own command pointer. The transfer destination is, for example, a response board, and the information for specifying the command pointer of the transfer destination or the transfer destination command pointer identifier is, for example, a command pointer number of a command pointer of the response board.

The physical protocol control unit 52 and the DMA control unit 57 in FIG. 1 correspond to the physical protocol control unit 69 and the DMA control unit 75 in FIGS. The DMA control means 57 may be provided outside the bus controller.

The message control means 55 and the command pointer control means 56 correspond to the message control unit 72 shown in FIGS. 2 and 6, and the transfer destination command pointer identifier storage means 58 includes the data memory 65-1 shown in FIGS. 65-2
Is equivalent to This transfer destination command pointer identifier storage means 58 may be provided inside the bus controller.

[0045]

The transmission buffer 53 of the request board requesting the transfer
Is transmitted onto the system bus 41 via the physical protocol control means 52, and the received message received from the system bus 41 is stored in the reception buffer 54 via the physical protocol control means 52. You.

The message control means 55 fetches the information (own command pointer identifier) for designating the own command pointer in response to a request from a CPU (not shown), and retrieves the own command designated by the information. Refers to its own command structure pointed to by the pointer. Then, an identifier of the transfer destination (response board) of the message is obtained from the own command structure, and a transmission message including the identifier is generated on the transmission buffer 53.
The command pointer control means 56 adds information for specifying the transfer destination command pointer (transfer destination command pointer identifier) when the transmission message is generated.

Thus, the transmission message including the command pointer identifier of the transfer destination is sent out onto the system bus 41 by the physical protocol control means 52 and sent to the response board.

In the response board receiving this transmission message, the command pointer identifier of the transfer destination included in the message is extracted, and the command of the transfer destination pointed to by the command pointer of the transfer destination specified by the command pointer identifier is extracted. The structure is referenced.
Then, the transfer requested by the request board is performed using the message buffer specified by the command structure of the transfer destination.

As described above, since the requesting board holds its own command pointer identifier and the command pointer identifier of the transfer destination separately, a command pointer identifier different from its own command pointer identifier is used as the command pointer identifier of the response board of the transfer destination. Can be specified. Therefore, the request board and the response board can voluntarily and arbitrarily determine their own command pointer numbers.

Further, the request board can recognize the command pointer identifier set by the response board voluntarily, and use the command pointer identifier as the command pointer identifier of the transfer destination.

The DMA control means 57 fetches the identifier of the response board, the command pointer identifier of the transfer destination, and the like from the memory, and passes them to the message control means 55. The request board transfer destination command pointer identifier storage means 58 stores a transfer destination command pointer identifier specified by the request board,
Alternatively, the command pointer identifier of the transfer destination read from the response board is stored.

[0052]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 2 is a configuration diagram of a CPU board that performs bus transfer according to the first embodiment of this invention. The CPU board 61 shown in FIG.
PU62, data memory 6 with message buffer
5-1, and a bus controller 67-1. C
The PU board 61 is connected to another CPU board (not shown), a memory board, an IO board, and the like via a system bus 64 to form a multiprocessor system.

The bus controller 67 includes a CPU controller 6
8, a physical protocol control unit 69, a memory control unit 78, a transmission buffer 71, a reception buffer 79, a message control unit 72, and a DMA control unit 75.

The physical protocol control section 69 has its own board ID register 70 for storing a board identifier (board ID) of the CPU board 61, and the DMA control section 75 has an address register for holding an address of the data memory 65-1. 76, and a data length register 77 for holding the data length of data exchanged between the data memory 65-1. Address register 76 and data length register 77
Are provided for writing to the data memory 65-1 and for reading from the data memory 65-1.

The message control section 72 has a vector register 74 and a self-command pointer number register 73, and performs protocol control such as generation and analysis of a message. The vector register 74 holds the start address of the command pointer table 66 stored in the data memory 65-1, and the own command pointer number register 73 stores
It holds its own command pointer number as an offset when accessing the command pointer table 66 in its own data memory 65-1.

The data memory 65-1 has a command pointer table 66 having a plurality of command pointers,
A plurality of board command blocks corresponding to each command pointer are stored. A plurality of board commands of each board command block are stored in combination with a board ID, a command pointer number, and a buffer command address, and a plurality of buffer command blocks are stored corresponding to each buffer command address. Each buffer command block stores a plurality of sets of buffer commands, buffer addresses, and data lengths.

FIG. 10 shows, as an example, a command pointer table 66 having a command pointer 0, a command pointer 1, and a command pointer 2. The board command block indicated by the command pointer 0 stores the board command 0, the board ID 0, the command pointer number 0, the buffer command address 0, and the like in order. The buffer command block indicated by the buffer command address 0 includes the buffer command 0 , Buffer address 0, data length 0 and the like are stored in order. Buffer address 0 is the address of message buffer 0, and buffer address 1 is the address of message buffer 1.

The message control unit 72 adds the command pointer number held by the self-command pointer number register 73 to the address held by the vector register 74 to obtain the storage address of the corresponding command pointer.
The corresponding board command block is accessed using the obtained command pointer.

In the first embodiment, an area for storing the command pointer number of the response board in addition to the board command, the board ID and the buffer command address is provided in the board command block. The request board requesting the message transfer can set the command pointer number of the response board to which the request message is transferred in the command pointer number area.

FIG. 3 is a flowchart showing the operation of the request board in the first embodiment. Request Board CP
Prior to the message transfer, U62 first reads the command pointer number from the self-command pointer number register 73 of the response board of the transfer destination, and holds the command pointer number as A (step S1).

Next, a corresponding command pointer is obtained using the address held by the vector register 74 of the response board and the read command pointer number, and the board command block indicated by the command pointer is checked. Then, the buffer command block indicated by each buffer command address included in the board command block is checked, and the data length included in the buffer command block is read (step S2).

Next, a message buffer having a size corresponding to the read data length is stored in the data memory 6 of the request board.
5-1 is secured (step S3), and the buffer address and data length (buffer size) of the secured buffer are set in the buffer command block in the same data memory 65-1 (step S4). Then, the address of the configured buffer command block is registered in the buffer command address in the board command block.

Here, whether the data length in the buffer command block indicated by all the buffer command addresses included in one board command block of the response board has been read, and whether all the corresponding buffers have been set in the request board or not. It is determined whether or not it is (step S5).
If the setting of all buffers has not been completed, the processing from step S2 is repeated to prepare the next buffer.

When the setting of all the buffers is completed, next, the held command pointer number A is written into the position corresponding to the buffer command address in the board command block (step S6), and the board ID of the response board is further written. Write to the corresponding position in the board command block (step S7). Then, the address of the configured board command block is registered as an unused command pointer in the command pointer table 66 (step S8).

Here, it is determined whether or not the preparation of the necessary message buffers for all the response boards of the transfer destination is completed, and the buffer command block, the board command block, and the command pointer table 66 in which these are registered have been constructed ( Step S9). If the setting of all the transfer destinations is not completed, the processing after step S1 is repeated for the next response board, and the processing is completed when the setting of all the transfer destinations is completed.

In this way, arbitrary command pointer numbers in a plurality of response boards are put together and registered in one command pointer in the command pointer table 66 of the request board. The CPU 62 of the request board stores the command pointer number designating this command pointer in its own command pointer number register 7 in the bus controller 67.
3 to cause the bus controller 67 to perform message transfer.

CPU control unit 6 in bus controller 67
When 8 receives the message transfer command from the CPU 62, the message control unit 72 adds the command pointer number held in the self-command pointer number register 73 to the address held in the vector register 74. Then, the command pointer stored at the address obtained as a result is taken out, the board command and the buffer command sequentially obtained from the board command block pointed to by the command pointer are analyzed, and the message transfer is controlled.

If the board command is an end command, the transfer is terminated. If the board command is invalid, the transfer to the next board command is skipped. If it is a write command, the board ID stored following the board command is set as a transfer destination, and the stored command pointer number is added after the board ID, and a write request message is generated on the transmission buffer 71. If the command is a read command, the board ID stored after the board command is set as a transfer destination, and the command pointer number stored after the board ID is added to generate a read request message on the transmission buffer 71.

The physical protocol control unit 69 converts the request message generated by the message control unit 72 into a transfer protocol specific to the system bus 64 and sends it out, and performs data transfer with the transfer destination board. When the transfer is completed, the physical protocol controller 69 notifies the CPU controller 68 of the completion of the transfer.

FIG. 4 is a timing chart of the message transfer in the first embodiment. The write request message sent from the request board to the system bus 64 includes, for example, a board ID, a self-board ID, a write request, and a command pointer number as shown in FIG. The read request message includes a board ID, a self-board ID, a read request, and a command pointer number, for example, as shown in FIG.

The message control unit 72 analyzes the next board command if the extracted buffer command is an end command, and skips to the next buffer command if it is an invalid command. If it is a transfer command, the buffer address and the data length stored following the buffer command are set in the DMA control unit 75.

The DMA controller 75 reads data from the message buffer in the data memory 65-1 and stores it in the transmission buffer 71 in the case of write transfer, and stores the received data in the reception buffer 79 in the case of read transfer. 65-1 in the message buffer.
The data stored in the transmission buffer 71 is sent to the transfer destination board by the physical protocol control unit 69.

On the other hand, in the transfer destination CPU board 61, the bus controller 67 compares the board ID of the transmission destination of the signal transmitted on the system bus 64 with the board ID stored in the self board ID register 70. If they match, the physical protocol control unit 69 stores the received message in the reception buffer 79.

The message control unit 72 adds the command pointer number added to the received write request message or read request message to the address held by the vector register 34, and adds the address of one command pointer in the command pointer table 66. Ask for.
Then, the board command and the buffer command sequentially obtained from the command pointer stored at the address are analyzed, and the message transfer is controlled.

If the board command is an end command, the transfer is terminated. If the board command is invalid, the transfer to the next board command is skipped. If it is a write command or a read command, the corresponding buffer command is analyzed.
If the buffer command is the end command, the next board command is analyzed. If the buffer command is invalid, the process skips to the next buffer command. If it is a transfer command, the buffer address and the data length stored following the buffer command are set in the DMA control unit 75.

If the received message is a write request message, a write permission message to be sent to the request board is generated on the transmission buffer 71. The DMA control unit 75 stores the data received in the reception buffer 79 in the message buffer in the data memory 65-1 when responding to the write request, and stores the data in the message buffer in the data memory 65-1 when responding to the read request. , And stores the data in the transmission buffer 71. The write permission message and data stored in the transmission buffer 71 are sent to the request board by the physical protocol control unit 69.

As shown in FIG. 4A, the write permission message transmitted from the response board to the system bus 64 in response to the write request message includes the board ID of the request board and the write permission. Also, upon receiving the write permission message, the request board sends the system bus 64
The data message sent above consists of the board ID of the response board and the data.

As shown in FIG. 4B, the data message transmitted from the response board to the system bus 64 in response to the read request message includes the board ID of the request board and data.

As described above, the request board can secure its own message buffer according to the size of the message buffer of the response board. Since the request board generates a request message using the command pointer number specified by the response board, the request board and the response board can use any command pointer number by setting it in the self-command pointer number register 73. become.

In the flow shown in FIG. 3, the request board reads the data length of the buffer from the response board and uses it. However, the request board can specify the data length for the response board.

FIG. 5 is a timing chart of the configuration message transfer performed when the request board specifies the data length of the buffer. In this case, prior to the transfer of the data message, the request board sends a configuration request message to the response board of the transfer destination, and requests a configuration of a command structure such as a board command block or a buffer command block.

The configuration request message includes, for example, the board ID of the response board, the board ID of the request board, the configuration request, the buffer address of the message buffer in the response board, and the data length (buffer size).

The response board receiving the configuration request message checks the buffer address and the data length specified by this, and if available, secures an unused command pointer number that has not been used yet. . Then, a board command block corresponding to the command pointer number is set, and the received buffer address and data length are set in the buffer command block indicated by the buffer command address therein.

Next, the response board generates a configuration response message to which the secured command pointer number is added, and transmits the configuration response message to the request board. The configuration response message includes, for example, the board ID of the request board, the board ID of the response board, the configuration response, and the command pointer number of the response board.

The request board that has received the configuration response message secures an unused command pointer number that has not been used yet, and stores the board ID and command pointer of the received response board in the board command block corresponding to the command pointer number. Set the number. Further, the buffer address and the data length of the message buffer in the request board used for transfer are set in the buffer command block indicated by the buffer command address in the board command block.

By the above configuration message transfer, the command pointer number of the response board is registered in the board command block of the request board, and the data message can be transferred using the command pointer number. The transfer of the data message is performed in the same manner as described above.

If the configuration message transfer is used, the response board can secure its own message buffer according to the size of the buffer specified by the request board.

Instead of sending the configuration request message, the request board writes the buffer address and the data length of the message to be transferred in the response board in the data memory 65-1 of the response board, and sends the command structure to the response board. You can also ask.
In this case, the request board reads and confirms the command pointer number secured by the response board from the data memory 65-1, and configures its own command structure using it.

FIG. 6 is a block diagram of a CPU board for performing bus transfer according to the second embodiment of the present invention. 6, the same components as those in FIG. 2 are denoted by the same reference numerals as in FIG. In the CPU board 61 of FIG.
The buffer area 5-2 is divided into a plurality of data modules, and the start address of each data module is registered in the data module pointer table 80 as a data module pointer.

Here, as an example, data module 0 and data module 1 are provided in data memory 65-2, and data module pointer 0 pointing to them is provided.
And the data module pointer 1 are stored in the data module pointer table 80.

FIG. 7 is a timing chart of the configuration message transfer in the second embodiment. In the first embodiment of FIG. 5, the request board specifies the buffer address and the data length by the configuration request message, but in the second embodiment, the data module number and the data length of the response board are specified instead. Request the configuration of the command structure.

The configuration request message shown in FIG. 7 includes, for example, the board ID of the response board, the board ID of the request board, the configuration request, the data module number to which the message buffer of the response board belongs, the buffer offset, and the data length (buffer size). ).

The response board that has received the configuration request message searches the data module pointer table 80 using the data module number designated by this, and obtains the corresponding data module pointer. Then, the received buffer offset is added to the head address of the data module indicated by the data module pointer to obtain the head address of the message buffer to be secured.

Next, an area corresponding to the data length received from the head address of the obtained message buffer is secured, and the message buffer is set. Then, an unused command pointer number not yet used is secured, and a board command block corresponding to the command pointer number is set. Also, the head address (buffer address) and data length of the message buffer are set in the buffer command block indicated by the buffer command address in the board command block.

In FIG. 6, message buffer 0 is set in data module 0, and message buffer 1 is set in data module 1. The buffer addresses and data lengths of these message buffers are buffer address 0 and data length 0, respectively.
The buffer address 1 and the data length 1 are set in the buffer command block.

Next, the response board generates a configuration response message to which the secured command pointer number is added, and transmits the configuration response message to the request board. The configuration response message includes, for example, the board ID of the request board, the board ID of the response board, the configuration response, and the command pointer number of the response board.

The operation of the request board receiving the configuration response message is the same as in the first embodiment. Thereafter, the data message is transferred in the same manner as in the first embodiment.

Instead of sending the configuration request message, the request board writes the data module number, buffer offset, and data length of the message to be transferred in the response board into the data memory 65-2 of the response board, You can also request the configuration of the command structure. In this case, the request board reads and confirms the command pointer number secured by the response board from the data memory 65-2, and configures its own command structure using the command pointer number.

In the first and second embodiments, the command structure (buffer command block, board command block, command pointer table, data module pointer table) for specifying the address and data length of the message buffer is stored in the data memory. Holding. However, the present invention is not limited to this, and the command structure may be built in the bus controller itself, or may be held in another storage location.

[0100]

According to the present invention, since the request board performs message transfer using the command pointer number registered in the response board, the request board and the response board can freely determine the command pointer number. Therefore, the command structure accessed by the command pointer number can be flexibly set, and the memory use efficiency is improved.

[Brief description of the drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a configuration diagram of a CPU board according to the first embodiment of the present invention.

FIG. 3 is a flowchart illustrating an operation of a request board in the first embodiment.

FIG. 4 is a timing chart of a message transfer in the first embodiment.

FIG. 5 is a timing chart of a configuration message transfer in the first embodiment.

FIG. 6 is a configuration diagram of a CPU board according to a second embodiment of the present invention.

FIG. 7 is a timing chart of a configuration message transfer in the second embodiment.

FIG. 8 is a diagram illustrating a configuration of a general information processing apparatus.

FIG. 9 is a diagram showing a configuration of a general CPU board.

FIG. 10 is a configuration diagram of a CPU board of the prior application.

FIG. 11 is a diagram showing a data relationship on the CPU board of the prior application.

FIG. 12 is a diagram showing a configuration of a board command.

FIG. 13 is a diagram showing a configuration of a buffer command.

[Explanation of symbols]

 1, 21, 61 CPU board 2 Memory board 3 IO board 4, 24, 51, 64 System bus 11, 22, 62 CPU 12 Program memory 13, 25, 65-1, 65-2 Data memory 14, 27, 67 bus Controllers 15, 23, 63 Internal bus 26 Group address table 28, 68 CPU control unit 29, 69 Physical protocol control unit 30, 70 Self-board ID register 31, 53, 71 Transmission buffer 32, 72 Message control unit 33 Group number register 34 , 74 Vector register 35, 75 DMA control unit 36, 76 Address register 37, 77 Data length register 38, 78 Memory control unit 39, 54, 79 Receive buffer 52 Physical protocol control unit 57 DMA control unit 55 Message control unit 56 Command pointer control unit 58 destination command pointer identifier storage means 66 command pointer table 73 self command pointer number register

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Souichi Arai 1-1-1, Tanabe Nitta, Kawasaki-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fuji Electric Co., Ltd. (72) Inventor Noriaki Kawahara 1-Fujimachi, Hino-shi, Tokyo Fuji Fako (56) References JP-A-3-158952 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 13 / 28,15 / 16,15 / 177

Claims (12)

(57) [Claims] 1. An information processing apparatus for accessing a memory by a DMA method, processing data stored in the memory, and performing a bus transfer by message passing via a system bus, wherein the transmission message transmitted to the system bus is provided. A physical protocol control unit for performing protocol control of a received message received from the system bus; a transmission buffer connected to the physical protocol control unit for storing the transmission message; a transmission buffer connected to the physical protocol control unit; A reception buffer for storing a message, and information for designating its own command pointer pointing to its own command structure, and referring to the own command structure, the transmission message including an identifier of a message transfer destination. Is generated on the transmission buffer. Bus controller, characterized in that it comprises a chromatography di controlling means, and a command pointer control means information for specifying the destination of the command pointer that points to the command structure in the transfer destination added to the transmission message. 2. A transfer destination command for storing a transfer destination command pointer identifier used to specify a storage area of the transfer destination command pointer in the transfer destination as information for specifying the transfer destination command pointer. 2. The transmission message according to claim 1, further comprising a pointer identifier storage unit, wherein the command pointer control unit adds the transfer destination command pointer identifier stored in the transfer destination command pointer identifier storage unit to the transmission message. Bus controller. 3. The message control means further comprising: DMA control means for extracting data from the memory by a DMA method, transferring the data to the transmission buffer, and storing data transferred from the reception buffer in the memory by a DMA method. 2. The bus controller according to claim 1, wherein said bus controller controls said DMA control means. 4. The memory holds a command pointer table holding the own command pointer, and a transfer destination command pointer identifier pointed to by the own command pointer and designating the transfer destination command pointer. The message control means stores the own command structure and the own message buffer pointed to by the own command structure, and stores the own command pointer identifier as information for designating the own command pointer. Self command pointer identifier storage means; and vector register means for storing the address of the command pointer table. The command pointer table and the own command structure are stored using the self command pointer identifier storage means and the vector register means. , And generates the transmission message according to the command included in the own command structure. The command pointer control means adds the transfer destination command pointer identifier held by the own command structure to the transmission message. Claim 3 characterized by the following:
Bus controller as described. 5. The own command structure is pointed by the own command pointer, and includes a response board identifier that is the transfer destination identifier and the transfer destination command pointer identifier. 5. The bus controller according to claim 4, further comprising: a buffer command block pointed from the board command block, the buffer command block including an address of the message buffer. 6. The response board sets an address and a size of a message buffer of the response board in a buffer command block of the response board, registers the buffer command block of the response board in a board command block of the response board, and The address of the board command block of the board is registered in the command pointer of the response board, the request board sets the address and size of the message buffer of the board in the buffer command block of the board, and stores the buffer command block of the board in the self. Registering the own board command block in the own command pointer, reading the transfer destination command pointer identifier from the response board, storing the identifier in the own board command block, Said command pointer control means board, C
According to a message transfer command from a PU, the transfer destination command pointer identifier stored in the board command block of the own board is taken out and added to a write request message or a read request message. 6. A write request message or a read request message is transmitted to the response board.
Bus controller as described. 7. The request board sets the address and size of its own message buffer in its own buffer command block, registers its own buffer command block in its own board command block,
Registering the own board command block in the own command pointer, the response board sets the address and size of the message buffer of the response board in the buffer command block of the response board, and responds to the buffer command block of the response board. Registering in the board command block of the board, registering the address of the board command block of the response board in the command pointer of the response board, and controlling the command pointer of the request board by C
According to a message transfer command from a PU, the transfer destination command pointer identifier stored in the board command block of the own board is taken out and added to a write request message or a read request message. 6. A write request message or a read request message is transmitted to the response board.
Bus controller as described. 8. The request board sets the address and size of its own message buffer in its own buffer command block, registers its own buffer command block in its own board command block,
Registering the own board command block in the own command pointer, notifying the address and size of the message buffer of the response board to the response board by a configuration request message, and requesting the configuration of the command structure of the response board, The response board sets the notified address and size of the message buffer of the response board in the buffer command block of the response board, registers the buffer command block of the response board in the board command block of the response board, Register the board command block in the command pointer of the response board, and notify the request board of the transfer destination command pointer identifier for designating the command pointer of the response board by a configuration response message, The request board stores the notified transfer destination command pointer identifier in its own board command block, and the command pointer control means of the request board
According to a message transfer command from a PU, the transfer destination command pointer identifier stored in the board command block of the own board is taken out and added to a write request message or a read request message. 6. A write request message or a read request message is transmitted to the response board.
Bus controller as described. 9. The request board sets the address and size of its own message buffer in its own buffer command block, registers its own buffer command block in its own board command block,
Registers its own board command block in its own command pointer, writes the address and size of the message buffer of the response board to the memory of the response board, and writes the address of the written message buffer of the response board to the response board. And setting the size in the buffer command block of the response board, registering the buffer command block of the response board in the board command block of the response board, registering the board command block of the response board in the command pointer of the response board, The board reads the transfer destination command pointer identifier for designating the command pointer of the response board and stores the read command identifier in its own board command block.
According to a message transfer command from a PU, the transfer destination command pointer identifier stored in the board command block of the own board is taken out and added to a write request message or a read request message. 6. A write request message or a read request message is transmitted to the response board.
Bus controller as described. 10. The request board has its own data module to which its own message buffer belongs and its own data module pointer pointing to the own data module, and uses its own data module pointer to write its own data module pointer. The address and size of the message buffer are obtained, the address and size of the own message buffer are set in the own buffer command block, the own buffer command block is registered in the own board command block, and the own board Register the command block in the own command pointer, and configure the buffer offset, the size of the own message buffer, and the data module identifier of the data module of the response board to which the message buffer of the response board belongs. A response request message to the response board, requesting a configuration of a command structure of the response board, the response board using a data module pointer of the response board corresponding to the notified data module identifier and the buffer offset. The address of the message buffer of the response board is obtained, the size of the own message buffer is set as the size of the message buffer of the response board, and the address and size of the message buffer of the response board are set in the buffer command block of the response board. Then, the buffer command block of the response board is registered in the board command block of the response board, the board command block of the response board is registered in the command pointer of the response board, and the command pointer of the response board is designated. Notifying the request board of the transfer destination command pointer identifier by a configuration response message to the request board, the request board stores the notified transfer destination command pointer identifier in its own board command block, The command pointer control means includes:
According to a message transfer command from a PU, the transfer destination command pointer identifier stored in the board command block of the self is taken out and added to a write request message or a read request message, and the physical protocol control means of the request board is 6. A write request message or a read request message is transmitted to the response board.
Bus controller as described. 11. The request board has its own data module to which its message buffer belongs and its own data module pointer that points to its own data module, and uses its own data module pointer to write its own data module pointer. The address and size of the message buffer are obtained, the address and size of the own message buffer are set in the own buffer command block, the own buffer command block is registered in the own board command block, and the own board A command block is registered in the own command pointer, and the buffer offset, the size of the own message buffer, and the data module identifier of the data module of the response board to which the message buffer of the response board belongs are stored in the response board. The response board obtains an address of a message buffer of the response board by using the data module pointer of the response board corresponding to the written data module identifier and the buffer offset, and obtains the message of the self. The buffer size is set to the size of the message buffer of the response board, the address and size of the message buffer of the response board are set in the buffer command block of the response board, and the buffer command block of the response board is set to the board command block of the response board. Registering, registering a board command block of the response board in a command pointer of the response board, the request board reads the transfer destination command pointer identifier for designating the command pointer of the response board Stored in the board command block of said self, the command pointer control unit of the request board, C
According to a message transfer command from a PU, the transfer destination command pointer identifier stored in the board command block of the self is taken out and added to a write request message or a read request message, and the physical protocol control means of the request board is 6. A write request message or a read request message is transmitted to the response board.
Bus controller as described. 12. Information for designating its own command pointer pointing to its own command structure and information for designating a transfer destination command pointer to point to a command structure at a message transfer destination are stored. Referring to the own command structure, generating a transmission message including the identifier of the transfer destination, adding information for designating the command pointer of the transfer destination to the transmission message, and transmitting the message to the transfer destination. A bus transfer method.