JPH08190523A - Bus controller and bus transfer method - Google Patents

Abstract

PURPOSE: To provide a bus controller and a bus transfer method to improve the memory use efficiency for an information processor to which plural boards are connected via a system bus. CONSTITUTION: When a write request is received from a CPU 62 of a request board, a message control part 72 takes out a command pointer that is designated by its on command pointer number register 73 included in a command pointer table 66 pointed by a vector register 74, and successively has accesses to a board command block and a buffer command block based on the command pointer. The ID of an answer board and a command pointer number are taken out of the board command block to add them to a request message and sends this message to the answer board. The part 72 of the answer board stores the received command pointer number in its own register 73 to obtain the message buffer that is used for transfer by means of the command pointer designated by the command pointer number, and controls a DMA control part 75.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus controller for controlling data transfer using a system bus in an information processing apparatus to which a plurality of boards are connected via the system bus.

[0002]

2. Description of the Related Art Today's information processing devices include a CPU (Centra).
l Processing Unit) In many cases, a system configuration is used in which multiple boards such as boards are connected by a system bus. In an information processing device configured using a system bus, the system configuration can be changed on a board-by-board basis, and a plurality of boards with different functions can be combined to flexibly build or expand the system. It is possible. In particular, a multiprocessor system capable of parallel processing can be realized by connecting a plurality of CPU boards with a system bus.

FIG. 8 is a block diagram of a general information processing apparatus. The information processing apparatus of FIG. 8 has a CPU board 1, a memory board 2 and an IO connected via a system bus 4.
(Input / Output) Board 3 and other boards. Each of these boards transfers data to other boards via the system bus 4.

FIG. 9 is a block diagram showing the internal structure of a general CPU board. CPU board 1 is CPU1
1, a program memory 12, a data memory 13, a bus controller 14, and an internal bus 15 connecting them.
Consists of The CPU 11 has a program memory 12
To read the data according to the command or to perform an operation on the read data and output the result of the operation. At this time, the CPU 11 reads the data from the data memory 13 in the CPU board 1 or the system bus 4 via the bus controller 14.
Read from. In addition, data is stored in the data memory 1
3 or send it to the system bus 4 via the bus controller 14.

In a multiprocessor system, the system bus 4 is occupied by the CPU board 1 while a certain CPU board 1 inputs / outputs data to / from the system bus 4. Cannot use the system bus 4. Therefore, it is important that the bus controller 14 efficiently control the input / output of data.

As a device for transferring data on the system bus of such an information processing device, a bus controller of a prior application using a message transfer system (Japanese Patent Application No. 6-264422).
3, filed on October 27, 1994).

FIG. 10 is a block diagram of a CPU board including the bus controller of this prior application. The CPU board 21 of FIG. 10 is a CPU 2 connected by an internal bus 23.
2, a data memory 25 having a message buffer, and a bus controller 27. CPU board 21
Are connected to other CPU boards (not shown), memory boards, IO boards, etc. by the system bus 24 to form a multiprocessor system.

The bus controller 27 is a CPU controller 2
8, a physical protocol control unit 29, a memory control unit 38, a transmission buffer 31, a reception buffer 39, a message control unit 32, and a DMA control unit 35.

The physical protocol controller 29 has a self-board ID register 30 for storing the board identifier (board ID) of the CPU board 21, and the DMA controller 35 has an address register 36 for holding the address of the data memory 25. , And a data length register 37 for holding the data length of the data exchanged with the data memory 25.
The address register 36 and the data length register 37 are provided with two sets, one for writing to the data memory 25 and the other for reading from the data memory 25.

The message controller 32 has a vector register 34 and a group number register 33, and performs protocol control such as message generation and analysis. The vector register 34 holds the start address of the group address table 26 stored in the data memory 25, and the group number register 33 stores the group address table 26.
Holds the group number as an offset when accessing.

The data memory 25 stores a group address table 26 having a group address 0, a group address 1 and a group address 2 and a plurality of groups of board commands corresponding to each group address. A plurality of board commands in each group are stored as a set with a board ID and a buffer command address, respectively, and a set of a plurality of buffer commands, buffer addresses, and data lengths is stored corresponding to each buffer command address. In FIG. 10, as an example, the board command of the group corresponding to the group address 0 is shown.

FIG. 11 shows an example of the structure of the data stored in the vector register 34 and the data memory 25 and the relationship between them. The vector register 34 is, for example, 0
The head address of the group address table 26 represented by 32 bits of 31 to 31 is stored, and the group address table 26 stores the addresses of a plurality of board commands represented by 32 bits, for example, as a group address.

The message control unit 32 accesses the group address table 26 using the address stored in the vector register 34 as the start address and the value of the group number stored in the group number register 33 as an offset. For example, when the group number is 0, the address of the board command 0-0 is fetched, when the group number is n, the address of the board command n-0 is fetched, and when the group number is m, the address of the board command m-0 is fetched. Take out.

Following the board command n-0 pointed to by the address of the board command n-0, the board ID n-
0, address of buffer command n-0-0, board command n-1, board ID n-1, buffer command n
Addresses such as -1-0 are stored. Also, the board command m pointed to by the address of the board command m-0
-0 followed by board ID m-0 and buffer command m
-0-0 address, board command m-1, board I
Addresses of Dm-1, buffer command m-1-0, etc. are stored. Similar storage structures are prepared for other groups. The addresses of these board commands, board IDs, and buffer commands are represented by 32 bits, for example.

Following the buffer command n-0-0 pointed to by the address of the buffer command n-0-0, the address of the buffer n-0-0, the data length of the buffer n-0-0, and the buffer command n- 0-1, buffer n-0
The address of -1, the data length of the buffer n-0-1 and the like are stored. Further, following the buffer command n-1-0 pointed to by the address of the buffer command n-1-0, the address of the buffer n-1-0 and the buffer n-1-
The data length of 0, the buffer command n-1-1, the address of the buffer n-1-1, the data length of the buffer n-1-1, etc. are stored. The same applies to the storage structure of other buffer commands. These buffer command, buffer address, and buffer data length are also represented by 32 bits, for example.

The address of buffer n-0-0 points to message buffer n-0-0 and the address of buffer n-0-1 points to message buffer n-0-1. The same applies to the addresses of other buffers. These message buffers have a size of 32 bits, for example.

FIG. 12 shows an example of the board command. The board command of FIG. 12 is represented by using 2 bits of 0 and 1 of the prepared 32 bits.
If these two bits are 00, it indicates the end command and 0
1 represents an invalid command, 10 represents a write command, and 11 represents a read command.

FIG. 13 shows an example of the buffer command. The buffer command shown in FIG.
It is represented using two bits, for example, 0 and 1 of the bits. If these two bits are 00, it represents an end command, 01 represents an invalid command, and 10 represents a transfer command.

When the CPU board 21 requests the transfer of data to / from another board, the CPU control unit 28 causes the CP
Upon receiving the message transfer request from U22, the message control unit 32 uses the values held by the group number register 33 and the vector register 34 to select one from the plurality of group addresses. Then, the board command and the buffer command which are sequentially obtained from the selected group address are analyzed, and the message transfer is controlled.

If the board command is an end command, the transfer is ended, and if it is an invalid command, the next board command is skipped. If it is a write command, a write request message is generated in the transmission buffer 31 with the board ID stored following the board command as the transfer destination. If it is a read command, a read request message is generated in the transmission buffer 31 with the board ID stored following the board command as the transfer destination.

The physical protocol control unit 29 converts the request message generated by the message control unit 32 into a transfer protocol specific to the system bus 24 and sends it out, and transfers data with the transfer destination board. When the transfer is completed, the physical protocol control unit 29 notifies the CPU control unit 28 of the completion of the transfer.

If the buffer command is an end command, the message controller 32 analyzes the next board command, and if it is an invalid command, skips to the next buffer command. If it is a transfer command, the buffer address and data length stored subsequent to the buffer command are set in the DMA control unit 35.

The DMA control unit 35 reads data from the message buffer in the data memory 25 and stores it in the transmission buffer 31 in the case of write transfer, and stores the data received in the receive buffer 39 in the data memory 25 in the case of read transfer. Stored in the message buffer of. The data stored in the transmission buffer 31 is sent to the transfer destination board by the physical protocol control unit 29.

When the CPU board 21 responds to data transfer with another board, the bus controller 27 sets the board ID of the transmission destination of the signal transmitted on the system bus 24 to its own board ID register. Compare with the board ID stored in 30. If they match, the message received by the physical protocol control unit 29 is stored in the reception buffer 39.

The message controller 32 uses the group number added to the received write request message or read request message and the value held by the vector register 34 to select one from a plurality of group addresses. Then, the board command and the buffer command which are sequentially obtained from the selected group address are analyzed, and the message transfer is controlled.

If the board command is an end command, the transfer is ended, and if it is an invalid command, the next board command is skipped. If it is a write command or a read command, the corresponding buffer command is analyzed.
If the buffer command is an end command, the next board command is analyzed, and if it is an invalid command, skip to the next buffer command. If it is a transfer command, the buffer address and data length stored subsequent to the buffer command are set in the DMA control unit 35.

If the received message is a write request message, a write permission message to be sent to the request board is generated on the transmission buffer 31. The DMA control unit 35 stores the data received in the reception buffer 39 in the message buffer in the data memory 25 when responding to the write request, and reads the data from the message buffer in the data memory 25 when responding to the read request. And stores it in the transmission buffer 31. Send buffer 3
The write permission message and data stored in 1 are sent to the request board by the physical protocol control unit 29.

As described above, the CPU board 21 of FIG.
In this case, the CPU 22 groups the board commands of a plurality of boards in advance and prepares them in the data memory 25, so that the board identifier of the specific group and the message buffer to be used are automatically specified only by specifying the group number. It is transmitted to the bus controller 27.
As a result, the bus controller 27 transfers the message to the designated plurality of response boards.

[0029]

However, the transfer method by the bus controller as described above has the following problems. In this method, both the request board requesting the transfer and the response board responding to the request operate using the group number designated by the group number register 33 of the request board. That is, the group address corresponding to the group number is obtained, the board command and the buffer command pointed to by the group address are analyzed, and the corresponding message buffer is used.

In this case, it is necessary to determine that the group numbers used in all the boards for message transfer do not overlap each other. For example, two different
Consider a case where two request boards 1 and 2 perform different message transfers to the same single response board.

First, the group numbers of the response board are continuously prepared from 0 to 9, and corresponding to these, the group addresses 0 to 9 are sequentially arranged in the group address table 26. Of these, the request board 1 performs the transfer using the group numbers 0 to 4 and the request board 2 performs the transfer using the group numbers 5 to 9.

At this time, the request board 1 does not use the values from the group number 5 to the group number 9, and the request board 2 does not use the values from the group number 0 to the group number 4. That is, among the commands such as board commands and buffer commands and other data arranged in the data memory 25, some data is not used, and the efficiency of use of the data memory 25 deteriorates.

The same applies when one request board performs different message transfers to two response boards 1 and 2 belonging to different groups. In this case, if the group number of the response board 1 is 0 and the group number of the response board 2 is 1, values other than the group number 0 are not used in the response board 1, and the response board 2
In, the values other than the group number 1 are not used. Therefore, a part of the command structure arranged in the data memory 25 is not used, and the use efficiency of the data memory 25 deteriorates.

It is an object of the present invention to provide a bus controller and a bus transfer method for efficiently transferring data in an information processing apparatus in which a plurality of boards are connected via a system bus and improving memory usage efficiency. And

[0035]

SUMMARY OF THE INVENTION The present invention relates to a bus in an information processing apparatus for accessing a memory by a DMA method, processing data stored in the memory, and performing bus transfer by message passing through a system bus. A controller and a bus transfer method.

FIG. 1 is a principle diagram of the bus controller of the present invention. The bus controller of FIG. 1 has physical protocol control means 52 and transmission buffer 5 as main components.
3, reception buffer 54, message control means 55, and command pointer control means 56.

The physical protocol control means 52 is connected to the system bus 51, and controls the protocol of the transmission message sent to the system bus 51 and the reception message received from the system bus 51.

Transmission buffer 53 and reception buffer 54
Is connected to the physical protocol control means 52 and stores the transmission message and the reception message, respectively. The message control means 55 stores information for designating its own command pointer pointing to its own command structure, and refers to the own command structure to transmit the transmission message including the identifier of the transfer destination of the message. It is generated on the buffer 53.

The command pointer control means 56 adds information for designating the command pointer of the transfer destination, which points to the command structure of the transfer destination, to the transmission message.

The bus controller of FIG. 1 further includes a DMA control means 57 and a transfer destination command pointer identifier storage means 58 as other components. DMA control means 57
Is controlled by the message control means 55, takes out data from the memory by the DMA method and transfers it to the transmission buffer 53, and stores the data transferred from the reception buffer 54 in the memory by the DMA method.

Transfer destination command pointer identifier storage means 5
Reference numeral 8 stores a transfer destination command pointer identifier used to specify the storage area of the transfer destination command pointer in the transfer destination as information for specifying the transfer destination command pointer. Then, the command pointer control means 56 adds the transfer destination command pointer identifier stored in the transfer destination command pointer identifier storage means 58 to the transmission message.

The information for designating the own command pointer is, for example, the command pointer number of the own command pointer. The transfer destination is, for example, a response board, and the information for designating the command pointer of the transfer destination or the transfer destination command pointer identifier is, for example, the command pointer number of the command pointer of the response board.

The physical protocol control unit 52 and the DMA control unit 57 of FIG. 1 correspond to the physical protocol control unit 69 and the DMA control unit 75 of FIGS. The DMA control means 57 may be provided outside the bus controller.

The message control means 55 and the command pointer control means 56 correspond to the message control section 72 shown in FIGS. 2 and 6, and the transfer destination command pointer identifier storage means 58 is the data memory 65-1 shown in FIGS. 65-2
Equivalent to. This transfer destination command pointer identifier storage means 58 may be provided inside the bus controller.

[0045]

Operation: The transmission buffer 53 of the request board that requests the transfer
Is transmitted to the system bus 41 via the physical protocol control means 52, and the received message received from the system bus 41 is stored in the reception buffer 54 via the physical protocol control means 52. It

In response to a request from a CPU (not shown), the message control means 55 takes out information (own command pointer identifier) for designating its own command pointer, and own command designated by the information. It refers to its own command structure pointed to by the pointer. Then, the identifier of the transfer destination (response board) of the message is obtained from its own command structure, and the transmission message including it is generated in the transmission buffer 53.
The command pointer control means 56 adds information (command pointer identifier of transfer destination) for designating the command pointer of the transfer destination when the transmission message is generated.

In this way, the transmission message including the command pointer identifier of the transfer destination is sent out to the system bus 41 by the physical protocol control means 52 and sent to the response board.

In the response board which has received this transmission message, the command pointer identifier of the transfer destination included in the message is taken out, and the command of the transfer destination pointed to by the command pointer of the transfer destination designated by the command pointer identifier is fetched. The structure is referenced.
Then, the transfer requested by the request board is performed using the message buffer specified by the command structure of the transfer destination.

As described above, since the request board holds the command pointer identifier of its own and the command pointer identifier of the transfer destination separately, the command pointer identifier of the response board of the transfer destination different from its own command pointer identifier is used. Can be specified. Therefore, the request board and the response board can voluntarily and arbitrarily determine their own command pointer numbers.

Further, the request board can recognize the command pointer identifier voluntarily set by the response board and use the command pointer identifier as the command pointer identifier of the transfer destination.

The DMA control means 57 takes out the response board identifier, the command pointer identifier of the transfer destination, etc. from the memory and passes them to the message control means 55. The transfer destination command pointer identifier storage means 58 of the request board stores the transfer destination command pointer identifier designated by the request board,
Alternatively, the command pointer identifier of the transfer destination read from the response board is stored.

[0052]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 2 is a configuration diagram of a CPU board that performs bus transfer according to the first embodiment of the present invention. The CPU board 61 of FIG. 2 is C connected by an internal bus 63.
PU 62, data memory 6 having a message buffer
5-1 and a bus controller 67-1. C
The PU board 61 is connected to other CPU boards, memory boards, IO boards, and the like (not shown) by the system bus 64 to form a multiprocessor system.

The bus controller 67 is a CPU controller 6
8, a physical protocol control unit 69, a memory control unit 78, a transmission buffer 71, a reception buffer 79, a message control unit 72, and a DMA control unit 75.

The physical protocol control unit 69 has its own board ID register 70 for storing the board identifier (board ID) of the CPU board 61, and the DMA control unit 75 has an address register for holding the address of the data memory 65-1. 76 and a data length register 77 for holding the data length of data exchanged between the data memory 65-1. Address register 76 and data length register 77
Are provided for writing to the data memory 65-1 and for reading from the data memory 65-1.

The message control section 72 has a vector register 74 and a self command pointer number register 73, and performs protocol control such as message generation and message analysis. The vector register 74 holds the start address of the command pointer table 66 stored in the data memory 65-1, and the self command pointer number register 73 holds
It holds its own command pointer number as an offset when accessing the command pointer table 66 in its own data memory 65-1.

In the data memory 65-1, a command pointer table 66 having a plurality of command pointers,
A plurality of board command blocks corresponding to each command pointer are stored. The plurality of board commands in each board command block are stored as a set with a board ID, a command pointer number, and a buffer command address, and a plurality of buffer command blocks are stored corresponding to each buffer command address. Then, a plurality of sets of buffer commands, buffer addresses, and data lengths are stored in each buffer command block.

In FIG. 10, a command pointer table 66 having a command pointer 0, a command pointer 1 and a command pointer 2 is shown as an example. The board command block indicated by the command pointer 0 stores the board command 0, the board ID 0, the command pointer number 0, the buffer command address 0, and the like in order, and the buffer command block indicated by the buffer command address 0 stores the buffer command 0. , Buffer address 0, data length 0, etc. are stored in order. Buffer address 0 is the address of message buffer 0, and buffer address 1 is the address of message buffer 1.

The message control unit 72 adds the command pointer number held by the self command pointer number register 73 to the address held by the vector register 74 to obtain the storage address of the corresponding command pointer,
The obtained command pointer is used to access the corresponding board command block.

In the first embodiment, the board command block has an area for storing the command pointer number of the response board in addition to the board command, the board ID, and the buffer command address. The request board requesting the message transfer can set the command pointer number of the response board which is the transfer destination of the request message in this command pointer number area.

FIG. 3 is a flow chart showing the operation of the request board in the first embodiment. CP of request board
Prior to message transfer, the U 62 first reads the command pointer number from the self command pointer number register 73 of the response board of the transfer destination and holds the command pointer number as A (step S1).

Next, the corresponding command pointer is obtained using the address held in the vector register 74 of the response board and the read command pointer number, and the board command block pointed to by the command pointer is examined. Then, the buffer command block pointed to by each buffer command address included in the board command block is checked, and the data length included in the buffer command block is read (step S2).

Next, a message buffer having a size corresponding to the read data length is provided in the data memory 6 of the request board.
5-1 is secured (step S3), and the buffer address and data length (buffer size) of the secured buffer are set in the buffer command block in the same data memory 65-1 (step S4). Then, the address of the configured buffer command block is registered in the buffer command address in the board command block.

Whether the data length in the buffer command block indicated by all the buffer command addresses included in one board command block of the response board has been read out and all the corresponding buffers have been set in the request board have been read out. It is determined (step S5).
If the setting of all the buffers is not completed, the processing from step S2 onward is repeated to prepare the next buffer.

When the setting of all the buffers is completed, next, the held command pointer number A is written in the position corresponding to the buffer command address in the board command block (step S6), and the board ID of the response board is set. Write to the corresponding position in the board command block (step S7). Then, the address of the configured board command block is registered in the unused command pointer in the command pointer table 66 (step S8).

Here, it is judged whether or not the preparation of the necessary message buffers for all the response boards at the transfer destinations is completed and the buffer command block, board command block, and command pointer table 66 in which they are registered have been constructed ( Step S9). If the setting of all the transfer destinations is not completed, the process from step S1 is repeated for the next response board, and the process is ended when the setting of all the transfer destinations is completed.

In this way, arbitrary command pointer numbers in the plurality of response boards are collected and registered in one command pointer in the command pointer table 66 of the request board. The CPU 62 of the request board assigns the command pointer number designating this command pointer to the self command pointer number register 7 in the bus controller 67.
3, and causes the bus controller 67 to transfer the message.

CPU controller 6 in bus controller 67
When 8 receives the message transfer command from the CPU 62, the message control unit 72 adds the command pointer number held by the self command pointer number register 73 to the address held by the vector register 74. Then, the command pointer stored in the address obtained as a result is taken out, the board command and the buffer command sequentially obtained from the board command block pointed to by the command pointer are analyzed, and message transfer is controlled.

If the board command is an end command, the transfer is ended, and if it is an invalid command, the next board command is skipped. If it is a write command, the board ID stored following the board command is set as the transfer destination, the command pointer number stored subsequent to the board ID is added, and a write request message is generated on the transmission buffer 71. If it is a read command, the board ID stored following the board command is set as the transfer destination, the command pointer number stored subsequent to the board ID is added, and a read request message is generated on the transmission buffer 71.

The physical protocol control unit 69 converts the request message generated by the message control unit 72 into a transfer protocol specific to the system bus 64 and sends it out, and transfers data with the transfer destination board. When the transfer is completed, the physical protocol control unit 69 notifies the CPU control unit 68 of the completion of the transfer.

FIG. 4 is a timing chart of message transfer in the first embodiment. The write request message sent from the request board to the system bus 64 consists of a board ID, a self board ID, a write request, and a command pointer number, as shown in FIG. The read request message is composed of a board ID, a self board ID, a read request, and a command pointer number, as shown in FIG. 4B, for example.

The message control unit 72 analyzes the next board command if the fetched buffer command is an end command, and skips to the next buffer command if it is an invalid command. If it is a transfer command, the buffer address and data length stored subsequent to the buffer command are set in the DMA controller 75.

The DMA controller 75 reads data from the message buffer in the data memory 65-1 and stores it in the transmission buffer 71 in the case of write transfer, and stores the data received in the receive buffer 79 in the data memory in the case of read transfer. It stores in the message buffer in 65-1.
The data stored in the transmission buffer 71 is sent to the transfer destination board by the physical protocol control unit 69.

On the other hand, in the transfer destination CPU board 61, the bus controller 67 compares the board ID of the transmission destination of the signal transmitted onto the system bus 64 with the board ID stored in the self-board ID register 70. When they match, the message received by the physical protocol control unit 69 is stored in the reception buffer 79.

The message control unit 72 adds the command pointer number added to the received write request message or read request message to the address held by the vector register 34 to obtain the address of one command pointer in the command pointer table 66. Ask for.
Then, the board command and the buffer command sequentially obtained from the command pointer stored at the address are analyzed, and the message transfer is controlled.

If the board command is an end command, the transfer is ended, and if it is an invalid command, the next board command is skipped. If it is a write command or a read command, the corresponding buffer command is analyzed.
If the buffer command is an end command, the next board command is analyzed, and if it is an invalid command, the next buffer command is skipped. If it is a transfer command, the buffer address and data length stored subsequent to the buffer command are set in the DMA controller 75.

If the received message is a write request message, a write permission message to be sent to the request board is generated in the transmission buffer 71. The DMA control unit 75 stores the data received in the reception buffer 79 in the message buffer in the data memory 65-1 when responding to the write request, and the message buffer in the data memory 65-1 when responding to the read request. The data is read from and stored in the transmission buffer 71. The write permission message and data stored in the transmission buffer 71 are sent to the request board by the physical protocol control unit 69.

As shown in FIG. 4A, the write permission message sent from the response board to the system bus 64 in response to the write request message includes the board ID of the request board and the write permission. Also, in response to the write permission message, the system bus 64 is sent from the request board.
The data message sent out consists of the board ID of the response board and the data.

As shown in FIG. 4B, the data message sent from the response board to the system bus 64 in response to the read request message is composed of the board ID and data of the request board.

Thus, the request board can secure its own message buffer according to the size of the message buffer of the response board. Further, since the request board uses the command pointer number specified by the response board to generate the request message, the request board and the response board can use any command pointer number set in the self command pointer number register 73. become.

In the flow of FIG. 3, the request board reads the data length of the buffer from the response board and uses it. However, the request board can specify the data length to the response board.

FIG. 5 is a timing chart of the configuration message transfer performed when the request board specifies the data length of the buffer. In this case, the request board sends a configuration request message to the response board of the transfer destination prior to the transfer of the data message to request the configuration of the command structure such as the board command block and the buffer command block.

This configuration request message comprises, for example, the board ID of the response board, the board ID of the request board, the configuration request, the buffer address of the message buffer in the response board, and its data length (buffer size).

The response board which has received the configuration request message checks the buffer address and data length specified thereby, and if it can be used for message transfer, reserves an empty command pointer number which has not been used yet. . Then, the board command block corresponding to the command pointer number is set, and the received buffer address and data length are set in the buffer command block pointed to by the buffer command address.

Next, the response board generates a configuration response message to which the secured command pointer number is added and sends it to the request board. This configuration response message includes, for example, the board ID of the request board, the board ID of the response board, the configuration response, and the command pointer number of the response board.

The request board which has received the configuration response message secures an empty command pointer number which is not yet used, and the board command block and command pointer of the received response board are stored in the board command block corresponding to the command pointer number. Set the number. Further, the buffer address and the data length of the message buffer in the request board used for the transfer are set in the buffer command block pointed to by the buffer command address in the board command block.

By the above configuration message transfer, the command pointer number of the response board is registered in the board command block of the request board, and the data message can be transferred using it. Transfer of the data message is performed in the same manner as described above.

By using the configuration message transfer, the response board can secure its own message buffer according to the size of the buffer designated by the request board.

Instead of sending the configuration request message, the request board writes the buffer address and data length in the response board of the message to be transferred to the data memory 65-1 of the response board, and configures the command structure in the response board. You can also ask.
In this case, the request board reads the command pointer number secured by the response board from the data memory 65-1 and confirms it, and uses it to construct its own command structure.

FIG. 6 is a block diagram of a CPU board for bus transfer according to the second embodiment of the present invention. 6, components similar to those in FIG. 2 are designated by the same reference numerals as those in FIG. In the CPU board 61 of FIG. 6, the data memory 6
The buffer area 5-2 is divided into a plurality of data modules, and the start address of each data module is registered in the data module pointer table 80 as a data module pointer.

Here, as an example, the data module 0 and the data module 1 are provided in the data memory 65-2, and the data module pointer 0 that points to them.
The data module pointer 1 is stored in the data module pointer table 80.

FIG. 7 is a timing chart of configuration message transfer in the second embodiment. In the first embodiment of FIG. 5, the request board specifies the buffer address and the data length by the configuration request message, but in the second embodiment, the data module number and the data length of the response board are specified instead. And request the construction of the command structure.

The configuration request message of FIG. 7 is, for example, the board ID of the response board, the board ID of the request board, the configuration request, the data module number to which the message buffer in the response board belongs, the buffer offset, and the data length (buffer size). ) Consists of.

The response board which has received the configuration request message searches the data module pointer table 80 by using the data module number designated thereby, and obtains the corresponding data module pointer. Then, the received buffer offset is added to the start address of the data module indicated by the data module pointer to obtain the start address of the message buffer to be secured.

Next, an area corresponding to the received data length is secured from the top address of the obtained message buffer, and the message buffer is set. Then, an empty command pointer number which is not yet used is secured and a board command block corresponding to the command pointer number is set. Also, the head address (buffer address) and data length of the message buffer are set in the buffer command block pointed to by the buffer command address in the board command block.

In FIG. 6, the message buffer 0 is set in the data module 0, and the message buffer 1 is set in the data module 1. Further, the buffer address and the data length of these message buffers are buffer address 0 and data length 0, respectively.
Buffer address 1 and data length 1 are set in the buffer command block.

Next, the response board generates a configuration response message to which the secured command pointer number is added and sends it to the request board. This configuration response message includes, for example, the board ID of the request board, the board ID of the response board, the configuration response, and the command pointer number of the response board.

The operation of the request board which has received the configuration response message is the same as that of the first embodiment. After that, the data message is transferred in the same manner as in the first embodiment.

Instead of sending the configuration request message, the request board writes the data module number, buffer offset, and data length in the response board of the message to be transferred to the data memory 65-2 of the response board, You can also request to configure the command structure. In this case, the request board reads the command pointer number secured by the response board from the data memory 65-2 and confirms it, and uses it to construct its own command structure.

In the first and second embodiments described above, the command structure (buffer command block, board command block, command pointer table, data module pointer table) for designating the address and data length of the message buffer is stored in the data memory. Hold on. However, the present invention is not so limited and the command structure may be built into the bus controller itself or may be held in another storage location.

[0100]

According to the present invention, since the request board transfers the message using the command pointer number registered in the response board, the request board and the response board can freely determine the command pointer number. Therefore, the command structure accessed by the command pointer number can be flexibly set, and the memory usage efficiency is improved.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a configuration diagram of a CPU board according to the first embodiment of the present invention.

FIG. 3 is a flowchart showing an operation of a request board in the first embodiment.

FIG. 4 is a timing chart of message transfer in the first embodiment.

FIG. 5 is a timing chart of configuration message transfer in the first embodiment.

FIG. 6 is a configuration diagram of a CPU board according to a second embodiment of the present invention.

FIG. 7 is a timing chart of configuration message transfer in the second embodiment.

FIG. 8 is a diagram showing a configuration of a general information processing apparatus.

FIG. 9 is a diagram showing a configuration of a general CPU board.

FIG. 10 is a configuration diagram of a CPU board of the prior application.

FIG. 11 is a diagram showing a relationship of data in the CPU board of the prior application.

FIG. 12 is a diagram showing a structure of a board command.

FIG. 13 is a diagram showing a structure of a buffer command.

[Explanation of Codes] 1, 21, 61 CPU Board 2 Memory Board 3 IO Board 4, 24, 51, 64 System Bus 11, 22, 62 CPU 12 Program Memory 13, 25, 65-1, 65-2 Data Memory 14 , 27, 67 Bus controller 15, 23, 63 Internal bus 26 Group address table 28, 68 CPU control unit 29, 69 Physical protocol control unit 30, 70 Self-board ID register 31, 53, 71 Transmission buffer 32, 72 Message control unit 33 group number register 34, 74 vector register 35, 75 DMA control unit 36, 76 address register 37, 77 data length register 38, 78 memory control unit 39, 54, 79 receive buffer 52 physical protocol control unit 57 DMA control unit 55 message Control means 56 commands the pointer control unit 58 destination command pointer identifier storage means 66 command pointer table 73 self command pointer number register

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Soichi Arai 1-1, Tanabe Nitta, Kawasaki-ku, Kawasaki-shi, Kanagawa Fuji Electric Co., Ltd. (72) Inventor Noriaki Kawahara 1-Fujimachi, Hino, Tokyo Control Co., Ltd.

Claims (12)

[Claims] 1. An information processing apparatus for accessing a memory by a DMA method, processing data stored in the memory, and performing bus transfer by message passing through a system bus, wherein the transmission message is sent on the system bus. And a physical protocol control unit that performs protocol control of a received message received from the system bus, a transmission buffer that is connected to the physical protocol control unit and that stores the transmission message, and a physical buffer control unit that is connected to the physical protocol control unit. A reception buffer for storing a message; and information for designating an own command pointer that points to its own command structure, and referring to the own command structure, the transmission message including an identifier of a transfer destination of the message Message on the send buffer. Bus controller, characterized in that it comprises a chromatography di controlling means, and a command pointer control means information for specifying the destination of the command pointer that points to the command structure in the transfer destination added to the transmission message. 2. A transfer destination command for storing a transfer destination command pointer identifier used to specify a storage area of the transfer destination command pointer in the transfer destination as information for specifying the transfer destination command pointer. 2. The pointer identifier storage means is further provided, and the command pointer control means adds the transfer destination command pointer identifier stored in the transfer destination command pointer identifier storage means to the transmission message. Bus controller. 3. The message control means, further comprising DMA control means for extracting data from the memory by the DMA method, transferring the data to the transmission buffer, and storing the data transferred from the reception buffer in the memory by the DMA method. The bus controller according to claim 1, wherein the bus controller controls the DMA control means. 4. The memory holds a command pointer table holding the command pointer of its own and a transfer destination command pointer identifier for designating the command pointer of the transfer destination pointed by the command pointer of its own. The self command structure and a self message buffer pointed to by the self command structure are stored, and the message control means stores a self command pointer identifier as information for designating the self command pointer. It has self-command pointer identifier storage means and vector register means for storing the address of the command pointer table, and the self-command pointer identifier storage means and the vector register means are used to create the command pointer table and the self-command structure. To generate the transmission message according to a command included in the command structure of the self, and the command pointer control means adds the transfer destination command pointer identifier held by the command structure of the self to the transmission message. 4. The method according to claim 3,
Bus controller as described. 5. An own board command block, wherein the own command structure is pointed to by the own command pointer, and includes an identifier of a response board that is an identifier of the transfer destination and the transfer destination command pointer identifier. 5. A bus controller according to claim 4, characterized in that it includes its own buffer command block which is pointed to from its own board command block and which contains the address of said own message buffer. 6. The response board sets an address and a size of a message buffer of the response board in a buffer command block of the response board, registers the buffer command block of the response board in a board command block of the response board, and returns the response. The address of the board command block of the board is registered in the command pointer of the response board, the requesting board sets the address and size of the message buffer of its own in the buffer command block of its own, and sets the buffer command block of its own in the self The board command block of its own, the board command block of its own is registered in its own command pointer, the transfer destination command pointer identifier is read from the response board and stored in the board command block of its own, Said command pointer control means board, C
In response to a message transfer command from the PU, the transfer destination command pointer identifier stored in the board command block of its own is taken out and added to a write request message or a read request message, and the physical protocol control means of the request board is 6. A write request message or a read request message is transmitted to the response board.
Bus controller as described. 7. The request board sets the address and size of its own message buffer in its own buffer command block and registers the own buffer command block in its own board command block,
The own board command block is registered in the own command pointer, the response board sets the address and size of the message buffer of the response board in the buffer command block of the response board, and the response command buffer command block is returned. The board command block of the board is registered, the address of the board command block of the response board is registered in the command pointer of the response board, and the command pointer control means of the request board is C
In response to a message transfer command from the PU, the transfer destination command pointer identifier stored in the board command block of its own is taken out and added to a write request message or a read request message, and the physical protocol control means of the request board is 6. A write request message or a read request message is transmitted to the response board.
Bus controller as described. 8. The requesting board sets the address and size of its own message buffer in its own buffer command block, registers the own buffer command block in its own board command block,
Registering its own board command block in its own command pointer and notifying the response board of the address and size of the message buffer of the response board by a configuration request message to request the configuration of the command structure of the response board; The response board sets the notified address and size of the message buffer of the response board in the buffer command block of the response board, registers the buffer command block of the response board in the board command block of the response board, and A board command block is registered in the command pointer of the response board, and the transfer destination command pointer identifier for designating the command pointer of the response board is notified to the request board by a configuration response message, The request board stores the notified transfer destination command pointer identifier in its own board command block, and the command pointer control means of the request board is C
In response to a message transfer command from the PU, the transfer destination command pointer identifier stored in the board command block of its own is taken out and added to a write request message or a read request message, and the physical protocol control means of the request board is 6. A write request message or a read request message is transmitted to the response board.
Bus controller as described. 9. The request board sets the address and size of its own message buffer in its own buffer command block, registers the own buffer command block in its own board command block,
Registering its own board command block in its own command pointer, writing the address and size of the message buffer of the response board to the memory of the response board, the response board writing the address of the written message buffer of the response board And the size are set in the buffer command block of the response board, the buffer command block of the response board is registered in the board command block of the response board, the board command block of the response board is registered in the command pointer of the response board, and the request The board reads the transfer destination command pointer identifier for designating the command pointer of the response board and stores it in the board command block of its own, and the command pointer control means of the request board is C
In response to a message transfer command from the PU, the transfer destination command pointer identifier stored in the board command block of its own is taken out and added to a write request message or a read request message, and the physical protocol control means of the request board is 6. A write request message or a read request message is transmitted to the response board.
Bus controller as described. 10. The request board has its own data module to which its message buffer belongs and its own data module pointer pointing to its own data module. Obtain the address and size of the message buffer, set the address and size of the message buffer of its own in the buffer command block of its own, register the buffer command block of its own in the board command block of its own, and the board of its own A command block is registered in the own command pointer, and the buffer offset, the size of the own message buffer, and the data module identifier of the data module of the response board to which the message buffer of the response board belongs are configured. A response request message to the response board to request the configuration of the command structure of the response board, and the response board uses the data module pointer of the response board and the buffer offset corresponding to the notified data module identifier. The address of the message buffer of the response board, the size of the own message buffer is used as the size of the message buffer of the response board, and the address and size of the message buffer of the response board are set in the buffer command block of the response board. Then, the buffer command block of the response board is registered in the board command block of the response board, the board command block of the response board is registered in the command pointer of the response board, and the command pointer of the response board is designated. For notifying the transfer destination command pointer identifier to the request board by a configuration response message, the request board stores the notified transfer destination command pointer identifier in the board command block of its own, The command pointer control means is C
In response to a message transfer command from the PU, the transfer destination command pointer identifier stored in the board command block of its own is taken out and added to a write request message or a read request message, and the physical protocol control means of the request board is 6. A write request message or a read request message is transmitted to the response board.
Bus controller as described. 11. The request board has its own data module to which its message buffer belongs and its own data module pointer pointing to its own data module, and uses its own data module pointer to store its own data module. Obtain the address and size of the message buffer, set the address and size of the message buffer of its own in the buffer command block of its own, register the buffer command block of its own in the board command block of its own, and the board of its own A command block is registered in the own command pointer, and the buffer offset, the size of the own message buffer, and the data module identifier of the data module of the response board to which the message buffer of the response board belongs are stored in the response board. The response board obtains the address of the message buffer of the response board by using the data module pointer of the response board corresponding to the written data module identifier and the buffer offset, and writes the message of its own. The size of the buffer is set as the size of the message buffer of the response board, the address and size of the message buffer of the response board are set in the buffer command block of the response board, and the buffer command block of the response board is set as the board command block of the response board. Register, register the board command block of the response board to the command pointer of the response board, and the request board reads the transfer destination command pointer identifier for designating the command pointer of the response board Stored in the board command block of said self, the command pointer control unit of the request board, C
In response to a message transfer command from the PU, the transfer destination command pointer identifier stored in the board command block of its own is taken out and added to a write request message or a read request message, and the physical protocol control means of the request board is 6. A write request message or a read request message is transmitted to the response board.
Bus controller as described. 12. Information for designating a command pointer of its own pointing to its command structure and information for designating a command pointer of a transfer destination pointing to a command structure of a message transfer destination are stored. Generating a transmission message including the identifier of the transfer destination by referring to its own command structure, adding information for designating the command pointer of the transfer destination to the transmission message, and transmitting the message to the transfer destination Bus transfer method characterized by.