JP3130114B2 - Transfer data processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transfer data processing apparatus for receiving and processing data transferred from a host computer.

[0002]

2. Description of the Related Art Conventionally, as a transfer data processing apparatus of this kind, as shown in FIG.
(Central processing unit) 1, ROM (read only memory) 2 in which program data for CPU 1 to control each unit is stored, RAM for storing received data and the like
(Random access memory) 3, an I / F (interface) processing unit 4 for receiving data transferred from the host computer, for example, an I / O processing unit 5 for outputting print data to a printing mechanism, and the CPU 1 The ROM
2, an address decoder 6 for selecting the RAM 3, the I / F processing unit 4 and the I / O processing unit 5 when controlling the I / F processing unit 5, and transferring data transferred from the host computer by software processing to the I / F processing unit 4. Via C
PU1 sequentially performs reception processing, stores the received data in a reception buffer in the RAM by the selection of the RAM 3 by the address decoder 5, and stores R in the reception buffer between reception processing.
Data is extracted from the AM 3 and output to the I / O processing unit 5. Note that data transfer is performed via the data bus line 7 and address transfer is performed via the address bus line 8.

[0003]

However, if the data transferred from the host computer is sequentially received and processed by the CPU 1 as described above, the data cannot be received at a high speed. It becomes difficult to buffer a large amount of data, and since the CPU always intervenes in reception,
There was a problem that the burden on software of U became large.

Accordingly, an object of the present invention is to provide a transfer data processing device capable of buffering a large amount of data from a host computer in a short time and reducing the software load on the CPU.

[0005]

The invention corresponding to claim 1 is:
An interface processing unit that receives a strobe signal and data from a host computer ;
Instruct high-speed communication and end high-speed communication,
In response to a strobe signal when instructing software communication
Alternate busy and ack signals by software control
Data generated by the interface processing unit
Central processing unit that captures and stores the
And location, time of high-speed communication instruction by the central processing unit, an address signal generating means for generating an address signal indicative of a predetermined address at the timing of the system clock, time of high-speed communication instruction by the central processing unit <br/>, the strobe signal response to stop the generation of the busy signal is generated in the ACK signal in response to the address signal from the address signal generating means together with generating a busy signal, the end of the high-speed communication from the central processing unit
The ACK / busy generation means for stopping controlling the generation of the acknowledgment signal in response to an instruction provided, busy to the host computer
Busy status is signaled by the acknowledgment signal
Requests the next data, and the central processing unit
When a high-speed communication instruction is issued, the interface is independent of the central processing unit.
The data received by the
Direct using an address signal from the raw means
Stored at a predetermined address in memory by memory access control
And the high-speed communication is terminated by the central processing unit.
It is to shift from high speed communication to software communication .

[0006] Claim 2 corresponding invention claimed, the strobe signal and the command unit from the host computer, an interface processing unit for receiving the data formed by the data unit, scan
Static and dynamic memory and software
Commands high-speed communication and hardware communication, and terminates high-speed communication.
End, and when instructing software communication, the strobe signal
The busy signal and update are controlled by software in response to the
Alternately generate a receive signal and receive it at the interface processing unit.
The specified data of the dynamic memory
A central processing unit for storing the less, when high-speed communication Instructs <br/> Ru in the central processing unit, the scan timing of the system clock
Predetermined address to store command section in static memory
Generates an address signal indicating
Address signal generating means for generating an address signal indicating a predetermined address for storing the data unit in the memory, during high-speed communication instruction by the central processing unit <br/>, address signals as well as generates a busy signal in response to strobe signal In response to the address signal from the generating means, an ACK signal is generated to stop the generation of the busy signal, and the high-speed communication from the central processing unit ends.
An ACK / BI that controls the generation of an ACK signal according to an instruction
Provide a means for generating
Busy status is signaled by the acknowledgment signal
Requests the next data, and the central processing unit
When a high-speed communication command is issued, the address is independent of the central processing unit.
Die using an address signal from the
Interface by Rect memory access control
The command part of the data received by the processing part is static.
Store the data at a predetermined address in the memory and download the data part.
Stored at a predetermined address in the dynamic memory,
From the high-speed communication by the high-speed communication end instruction from the device.
Is to shift to hardware communication .

[0007]

According to the first aspect of the present invention, when high-speed transfer is instructed by the high-speed transfer instructing means, data received by the interface processing unit is stored at a predetermined address of the memory by direct memory access control. At that time, an address signal indicating a predetermined address is generated at the timing of the system clock, an ack signal is generated in response to the address signal, and the generation of the busy signal is stopped.

According to a second aspect of the present invention, when high-speed transfer is instructed by the high-speed transfer instructing means, the data received by the interface processing section is controlled by direct memory access control so that the command section and the data section have different addresses in the memory. Stored separately for each area. At that time, an address signal indicating each address area is generated at the timing of the system clock, an ack signal is generated in response to the address signal, and the generation of the busy signal is stopped.

[0009]

An embodiment of the present invention will be described below with reference to the drawings.

As shown in FIG. 1, a CPU 11 constituting a control section main body, a ROM 12 storing program data for controlling the respective sections by the CPU 11, a RAM 13 storing received data and the like, and data transferred from a host computer. An I / F processing unit 14 for performing a receiving process of, for example, an I / O processing unit 15 for outputting a signal for controlling a printing mechanism,
The CPU 11 controls the ROM 12, RAM 13, I / F
An address decoder 16 as an address signal generating means for selecting the processing unit 14 and the I / O processing unit 15 when performing control, and an ACK for generating an ACK (ACK) signal and a busy (BUSY) signal. / BUSY generation unit 17 is provided.

The CPU 11, ROM 12, RAM 13
Are connected via a data bus line 18 and an address bus line 19, and the CPU 11 is connected to the I / F processing unit 14 and the I / O processing unit 15 via the data bus line 18; The ACK / BUSY generator 17 is connected via an address bus line 19.

FIG. 2 shows a memory map, and 000000 (HEX)
32KB of 007FFF (HEX) is general-purpose ROM, 008000 (HEX)
EX) ~ 00FFFF (HEX) 32KB is general-purpose RAM, 0100
00 (HEX) is an I / F for extracting data from the I / F processing unit 14.
The / F register and 020000 (HEX) constitute a reception register for storing I / F data. The actual physical address of the reception register is incremented each time data is input. The value is from 000000 (HEX) to 7FFFFF (HEX) in the large-capacity RAM.
It is about 8 MByte.

The ACK / BUSY generating section 17 constitutes an ACK / busy generating means, and as shown in FIG.
D-type flip-flops 21, 22, 23, 24, 7
It is composed of the logic gate elements 23 to 29 and the inverter 30. Then, a signal of an address 17 indicating an address of 020000 (HEX) and a high-speed transfer flag (high-speed transfer instruction means) indicating a direct memory address are input to the logic gate element 23, and the system clock of the CPU 11 is changed to the clock of the flip-flop 21. An input terminal and a clock (CK) input terminal of the flip-flop 23 are input to the clock (CK) input terminal of the flip-flop 22 via an inverter 30. Further, the CPU 11 instructs the end of the direct memory access to direct memory access (DM
A) The end flag is input to the logic gate element 24 and to the D input terminal of the flip-flop 23. The Q output of the flip-flop 23 is input to the logic gate element 24, and the logic gate element 2
4 is input to the clear (CL) terminals of the flip-flops 21 and 22. A reset signal for returning the system to an initial value is input to a clear (CL) terminal of the flip-flop 23.

The Q output of the flip-flop 21 is input to the D input terminal of the flip-flop 22 at the next stage. The / Q outputs of the flip-flops 21 and 22 are input to the logic gate element 25, and the output of the logic gate element 25 and the software ACK output for software I / F control are applied to the logic gate element 2.
6 and outputs an ACK signal from the logic gate element 26.

A strobe signal for extracting data from the host computer is input to a clock (CK) input terminal of the flip-flop 24. Then, the / Q (negative logic Q) output of the flip-flop 24 and the software BUSY output for software I / F control are input to the logic gate element 29, and the logic gate element 29 outputs a BUSY signal. ing.

The high-speed transfer flag and the read signal are input to the logic gate element 27, and the logic gate element 27
And the ACK signal from the logic gate element 26 are input to the logic gate element 28, and the output of the logic gate element 28 is used to clear the flip-flop 24 (C
L) terminal.

The ACK / BU having the above configuration
The SY generator 17 operates at the timing shown in FIG.

In the software communication, the software exchanges commands with the host computer. By setting the high-speed transfer flag to low level as shown in FIG. 4 (g), the software ACK signal and the software BUSY signal are set. The signal will be selected.

As shown in FIG. 4A, a strobe signal is output near the center of the I / F data shown in FIG.
At the rising edge, the BUSY signal goes high, as shown in FIG.

The CPU 11 recognizes the generation of the strobe signal, and sets the software BUSY to a low level as shown in FIG. Then, as shown in FIG. 4 (l), the flip-flop 24 for generating a BUSY signal in hardware is initialized by a read signal for extracting data, but the BUSY signal remains high until the software BUSY goes high. Hold the level. The ACK signal shown in FIG. 4D is similarly controlled by the software ACK signal shown in FIG.

In high-speed communication, by setting the high-speed transfer flag to a high level as shown in FIG. 4G, the CPU 11 performs direct memory access control as shown in FIG. The strobe signal goes low, data is transferred from the host computer,
It is transferred to the area of the address 17, that is, the memory area of the RAM 13. (Means for storing at a predetermined address in the memory) Then, as shown in (i) of FIG. 4, at the timing of the system clock T1, the address 17 is output from the address decoder 16 as shown in (h) of FIG. 6.5 clock times for flip-flop 2
I make it with 1,22. (Address signal generating means) Also, the direct memory access end flag
When the signal is output at the timing indicated by the dotted line in (j), the ACK signal is not output as indicated by the dotted line in (d) of FIG. 4, and after the software recognizes the direct memory access end flag, As shown by the dotted line in (g), the high-speed transfer flag is set to low level to enable the software ACK and the software BUSY. Thus, the high-speed communication processing is completed, and the software communication is performed again.

As described above, the switching between the software communication and the high-speed communication is performed according to the level of the high-speed transfer flag. At this time, the switching between the ACK signal and the BUSY signal is performed in the processing status in which the BUSY signal is at the high level. No extra burden on the software.

By applying the direct memory access method to data storage from the I / F processing unit 14 to the reception register in the RAM 13 as described above, the CPU 11
The received data can be written to the reception register of the RAM 13 without going through the register. Then, the received data is RA
When writing to the reception register of M13, an ACK signal, B, which is an I / F control signal, is based on the address information to be written.
A USY signal can be output.

Therefore, even if a high-speed transfer process such as receiving a large amount of data in a short time by a simple control from the host computer is required, it can be sufficiently dealt with. In addition, the software load on the CPU 11 can be reduced.

Next, another embodiment of the present invention will be described with reference to the drawings. The same parts as those in the above embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 5, instead of the RAM 13, a static RAM 31 and a dynamic RAM 32 are used.
And a dynamic RAM control unit 33 for controlling the dynamic RAM 32 to write and read data. The address decoder 16 'causes the CPU 11 to control the ROM 12, the static RAM 31,
When controlling the I / F processing unit 14, the I / O processing unit 15, and the dynamic RAM control unit 33, they are selected.

The dynamic RAM controller 33 and the dynamic RAM 32 are connected via a data bus line 34 and an address bus line 35.

FIG. 6 shows a memory map. In addition to the memories of the above-described embodiment, in particular, 328000 of 048000 (HEX) to 04FFFF (HEX) are used.
A general-purpose RAM for I / F processing composed of KB is provided. A general-purpose RA consisting of 008000 (HEX) to 00FFFF (HEX)
M is composed of the static RAM 31 and the I /
The F processing general-purpose RAM corresponds to the static RAM 31.

In the I / F processing general-purpose RAM, by writing the command portion of the data under the direct memory access control of the CPU 11 in the high-speed communication, the ACK / B
The USY generation unit 17 generates an ACK signal and a BUSY signal.

Further, a CPU is connected to the dynamic RAM 32 via the dynamic RAM control unit 33 in the high-speed communication.
11 writes the data portion of the data in the direct memory access control, and the ACK / BUSY generation unit 17 outputs
A K signal and a BUSY signal are generated.

FIG. 7 shows a part of the address decoder 16 'and A
ACK / BUSY generation unit 17 shows the configuration,
The configuration of the / BUSY generation unit 17 is the same as that of FIG. Address 15, address 16,.
Input address 17 and address 18
Chip select signal (ROM CS), chip select signal (RAM CS) of each general purpose RAM, select signal of I / F register (I / F Reg.), Select signal of receive register (Rece
ive Reg.) is incorporated. The select signal (output of Y9) of the general-purpose RAM for I / F processing is input to the logic gate element 23.

The circuit of FIG. 7 operates at the timing shown in FIG. First, the data of the first command portion is received from the host computer by software communication by the CPU 11, and then the communication of the n-byte command portion is performed by setting the high-speed transfer flag to high level as shown in (j) of FIG. As a result, in the direct memory access control of the CPU 11, the static RAM 3
1 area.

As shown in FIG. 8A, a strobe signal is output near the center of the I / F data shown in FIG.
At the rising edge, the BUSY signal goes high as shown in FIG.

When direct memory access control is being performed, the high-speed transfer flag is at the high level as shown in FIG. 8 (j), and the CPU 11 detects the strobe signal to As shown in (e), the I / F register of 010000 (HEX) is accessed, and FIG.
The command is read at the timing shown in (k). This command is issued at the timing shown in FIG.
In the state following U11, the general-purpose RAM for I / F processing of 048000 (HEX) is accessed and written on the static RAM 31 of 008000 (HEX). At the same time, (d) and (c) of FIG.
As shown in (1), the generation of the ACK signal and the stop of the BUSY signal are performed.

FIG. 9 shows the operation timing in more detail. FIG. 9 is an enlarged view of a portion P indicated by a dashed line in FIG.

That is, the process of accessing the I / F register and reading the command is performed as shown in FIG.
, T2, TW, TW, TW, and T3. The process of accessing the general-purpose RAM for I / F processing and writing a command on the static RAM 31 is also performed by six system clocks.

The ACK signal generates a low-level time with a signal for 6.5 clocks. When the direct memory access control signal goes low after receiving the n-th byte command as shown in FIG. 8 (h), no ACK signal is generated from the address signal, and the software・ After recognizing the access control signal, the high-speed transfer flag is set to low level as shown in (j) of FIG. 8 to enable ACK and BUSY by software as shown in (l) and (m) of FIG. I do.

The above is the case of receiving the command part.
In the case of receiving an m-byte data portion, a completely similar sequence is performed as shown in FIG.
Data is stored in M32.

As described above, in the present embodiment, switching between software communication and high-speed communication is performed according to the level of the high-speed transfer flag, and the RA stored according to the command part or the data part.
M is used properly. As a result, the command part and the data part are stored in the static RAM 31 and the dynamic RAM, respectively.
Reception can be performed at high speed without burdening software by dividing the area into AM32.

Therefore, in this embodiment, the same effects as those of the above embodiment can be obtained. Also, switch the command section
The data is stored in the static RAM 31 and the data
The command part and data are stored in the dynamic RAM 32.
Data is stored in
Of the command section and data section when printing
The management is simplified, and the workload of the CPU 11 can be reduced.

It should be noted that the high-speed communication processing of the present invention
The present invention can also be applied to a case where data is output from the I / O processor 15 to the I / O processor 15 at a high speed. The protocol for receiving data from the host computer is ACK signal and BU
The present invention can be applied not only to a combination of SY signals but also to a combination of other signals.

[0042]

As described in detail above, according to the invention described in each claim , a large amount of data can be buffered from the host computer in a short time by a simple control , and the software load on the CPU is reduced. It is possible to provide a transfer data processing device capable of alleviating the problem. Also,
According to the second aspect of the present invention, the command part is further provided with a
Storing the data in the Tatic RAM and dynamizing the data
Read and print data by storing it in memory RAM
Address management of the command section and data section when performing
Simply, the workload of the central processing unit can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a view showing a memory map of the embodiment.

FIG. 3 is an exemplary diagram showing a specific circuit example of an ACK / BUSY generation unit in the embodiment.

FIG. 4 is a view showing operation timings of an ACK / BUSY generation unit in the embodiment.

FIG. 5 is a block diagram showing another embodiment of the present invention.

FIG. 6 is a view showing a memory map of the embodiment.

FIG. 7 shows a part of the address decoder and A in the embodiment.
The figure which shows the specific circuit example of a CK / BUSY generation part.

FIG. 8 shows a part of the address decoder and A in the embodiment.
The figure which shows the operation timing of a CK / BUSY generation part.

FIG. 9 is a diagram showing an operation timing in which FIG. 8 is partially enlarged;

FIG. 10 is a block diagram showing a conventional example.

[Explanation of symbols]

11 CPU, 12 ROM, 13 RAM, 14 I
/ F processing unit, 16, 16 '... address decoder, 17 ...
ACK / BUSY generation unit, 31 static RAM,
32 ... Dynamic RAM.

Claims (2)

(57) [Claims] An interface processing unit for receiving a strobe signal and data from a host computer, instructing software communication and high-speed communication, and instructing termination of high-speed communication. When software communication is instructed, software control is performed in response to the strobe signal. A central processing unit that alternately generates a busy signal and an ack signal and fetches the data received by the interface processing unit and stores the data at a predetermined address in a memory; Address signal generating means for generating an address signal indicating an address; and when a high-speed communication is instructed by the central processing unit, a busy signal is generated in response to a strobe signal and an acknowledge is generated in response to an address signal from the address signal generating means. Generate a signal An ack / busy generating means for stopping the generation of the busy signal and stopping the generation of the ack signal in response to the termination instruction of the high speed communication from the central processing unit is provided, and the busy state is notified to the host computer by the busy signal. The next data is requested by an ACK signal, and when high-speed communication is instructed by the central processing unit, the data received by the interface processing unit independently of the central processing unit is converted to an address signal from the address signal generating unit. Direct using
A transfer data processing device, wherein the data is stored at a predetermined address of the memory by memory access control, and the high speed communication is switched to the software communication in response to a high speed communication end instruction from the central processing unit. 2. An interface processing unit for receiving data formed by a strobe signal, a command part, and a data part from a host computer, a static memory and a dynamic memory, and instructing software communication and high-speed communication and terminating the high-speed communication. A central processing unit for generating a busy signal and an ack signal alternately by software control in response to a strobe signal in response to a strobe signal when instructing software communication, and taking in the data received by the interface processing unit and storing it at a predetermined address of the dynamic memory When a high-speed communication is instructed by the central processing unit, an address signal indicating a predetermined address for storing a command part in the static memory is generated at the timing of a system clock, and a data part is stored in the dynamic memory. Address signal generating means for generating an address signal indicating a predetermined address, and when a high-speed communication is instructed by the central processing unit, generates a busy signal in response to a strobe signal and responds to an address signal from the address signal generating means. Generating an ACK signal to stop the generation of the busy signal, and controlling the stop of the generation of the ACK signal by an end instruction of the high-speed communication from the central processing unit. The busy state is notified by a signal and the next data is requested by an ack signal. When the high speed communication is instructed by the central processing unit, the address signal from the address signal generating means is used independently of the central processing unit. Interface processing unit by direct memory access control The command part of the received data is stored at a predetermined address of the static memory, and the data part is stored at a predetermined address of the dynamic memory. From the high speed communication to the software communication in response to a high speed communication termination instruction from the central processing unit. A transfer data processing device characterized by shifting.