JPS6118789B2 - - Google Patents

Info

Publication number
JPS6118789B2
JPS6118789B2 JP15496877A JP15496877A JPS6118789B2 JP S6118789 B2 JPS6118789 B2 JP S6118789B2 JP 15496877 A JP15496877 A JP 15496877A JP 15496877 A JP15496877 A JP 15496877A JP S6118789 B2 JPS6118789 B2 JP S6118789B2
Authority
JP
Japan
Prior art keywords
input
computer
output device
computers
communication
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP15496877A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5487043A (en
Inventor
Yoichi Suzuki
Setsuo Kugimya
Akio Hanada
Teruyoshi Mita
Hiroshi Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15496877A priority Critical patent/JPS5487043A/ja
Publication of JPS5487043A publication Critical patent/JPS5487043A/ja
Publication of JPS6118789B2 publication Critical patent/JPS6118789B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Multi Processors (AREA)
JP15496877A 1977-12-22 1977-12-22 Communication system between plural computers and common input/output device Granted JPS5487043A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15496877A JPS5487043A (en) 1977-12-22 1977-12-22 Communication system between plural computers and common input/output device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15496877A JPS5487043A (en) 1977-12-22 1977-12-22 Communication system between plural computers and common input/output device

Publications (2)

Publication Number Publication Date
JPS5487043A JPS5487043A (en) 1979-07-11
JPS6118789B2 true JPS6118789B2 (enrdf_load_stackoverflow) 1986-05-14

Family

ID=15595822

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15496877A Granted JPS5487043A (en) 1977-12-22 1977-12-22 Communication system between plural computers and common input/output device

Country Status (1)

Country Link
JP (1) JPS5487043A (enrdf_load_stackoverflow)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56135224A (en) * 1980-03-25 1981-10-22 Nec Corp Interruption device

Also Published As

Publication number Publication date
JPS5487043A (en) 1979-07-11

Similar Documents

Publication Publication Date Title
JPH01162967A (ja) 割込み処理方法及び装置
JPS6118789B2 (enrdf_load_stackoverflow)
GB1570206A (en) Data processing system
JP3082297B2 (ja) タスク制御方式
JPS63153635A (ja) デ−タ転送速度指定方式
JPS61123244A (ja) デ−タ通信処理装置
JPS6239792B2 (enrdf_load_stackoverflow)
JPS6012668B2 (ja) ダイレクトメモリアクセス装置のインタ−フエイス回路
JPH06259376A (ja) データ転送装置
JPS6335141B2 (enrdf_load_stackoverflow)
JPS6149270A (ja) マルチプロセツサシステムの入/出力制御方式
JPS63228255A (ja) バス中継装置
JPS63265349A (ja) デ−タ転送制御装置
JPH0573484A (ja) 情報処理システム
JPH02310657A (ja) バス接続装置
JPH0728750A (ja) インターフェース変換装置
JPS6168665A (ja) 電子計算機における入出力制御装置
JPS61131154A (ja) デ−タ転送制御方式
JPS62109452A (ja) デ−タ通信制御装置
JPH03246654A (ja) データ転送制御方法
JPS6231386B2 (enrdf_load_stackoverflow)
JPH04160459A (ja) データ転送装置
JPS62145345A (ja) 直接メモリアクセス間隔制御方式
JPS5832425B2 (ja) マルチ構成処理装置におけるリセット方式
JPS6188351A (ja) プログラムロ−ド方式