JPS61170857A - マイクロコンピユ−タ装置 - Google Patents

マイクロコンピユ−タ装置

Info

Publication number
JPS61170857A
JPS61170857A JP1107185A JP1107185A JPS61170857A JP S61170857 A JPS61170857 A JP S61170857A JP 1107185 A JP1107185 A JP 1107185A JP 1107185 A JP1107185 A JP 1107185A JP S61170857 A JPS61170857 A JP S61170857A
Authority
JP
Japan
Prior art keywords
bus
signal
dmac
control unit
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1107185A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0431139B2 (enrdf_load_stackoverflow
Inventor
Giichi Shimizu
清水　儀一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP1107185A priority Critical patent/JPS61170857A/ja
Publication of JPS61170857A publication Critical patent/JPS61170857A/ja
Publication of JPH0431139B2 publication Critical patent/JPH0431139B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
JP1107185A 1985-01-25 1985-01-25 マイクロコンピユ−タ装置 Granted JPS61170857A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1107185A JPS61170857A (ja) 1985-01-25 1985-01-25 マイクロコンピユ−タ装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1107185A JPS61170857A (ja) 1985-01-25 1985-01-25 マイクロコンピユ−タ装置

Publications (2)

Publication Number Publication Date
JPS61170857A true JPS61170857A (ja) 1986-08-01
JPH0431139B2 JPH0431139B2 (enrdf_load_stackoverflow) 1992-05-25

Family

ID=11767743

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1107185A Granted JPS61170857A (ja) 1985-01-25 1985-01-25 マイクロコンピユ−タ装置

Country Status (1)

Country Link
JP (1) JPS61170857A (enrdf_load_stackoverflow)

Also Published As

Publication number Publication date
JPH0431139B2 (enrdf_load_stackoverflow) 1992-05-25

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