JPS61170200U - - Google Patents

Info

Publication number
JPS61170200U
JPS61170200U JP1985052285U JP5228585U JPS61170200U JP S61170200 U JPS61170200 U JP S61170200U JP 1985052285 U JP1985052285 U JP 1985052285U JP 5228585 U JP5228585 U JP 5228585U JP S61170200 U JPS61170200 U JP S61170200U
Authority
JP
Japan
Prior art keywords
decoder
circuit
lines
outputs
word lines
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1985052285U
Other languages
English (en)
Other versions
JPH051040Y2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1985052285U priority Critical patent/JPH051040Y2/ja
Priority to US06/849,630 priority patent/US4870618A/en
Publication of JPS61170200U publication Critical patent/JPS61170200U/ja
Application granted granted Critical
Publication of JPH051040Y2 publication Critical patent/JPH051040Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C29/50016—Marginal testing, e.g. race, voltage or current testing of retention
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Read Only Memory (AREA)

Description

【図面の簡単な説明】
第１図は本考案によるＥＰＲＯＭの一実施例の
概略図、第２図はデータバツフア１および書込み
回路２の回路図、第３図はＹアドレスバツフア３
の回路図、第４図はＹデコーダ４の回路図、第５
図はＸアドレスバツフア５の回路図、第６図はＸ
デコーダ６の回路図である。 １……データバツフア、２……書込み回路、３
……Ｙアドレスバツフア、４……Ｙデコーダ、５
……Ｘアドレスバツフア、６……Ｘデコーダ、７
……Ｖｐｐ引き上げ回路、Ｖｐｐ……電源、Ｑ０
〜ＱＭ……ＮチヤンネルＭＯＳトランジスタ、Ｍ
１１〜ＭＮＭ……メモリーセル、Ｄ……データ入
力、Ｙ１〜Ｙｍ……Ｙアドレス入力、Ｘ１〜Ｘｎ
……Ｘアドレス入力、Ｄ１〜ＤＭ……デイジツト
線、Ｗ１〜ＷＮ……ワード線、Ｓ１，Ｓ２……テ
スト信号、ＳＹｊ……ｙ選択信号、ＳＸｋ……ｘ
選択信号、Ｉ１〜Ｉ４，Ｉ５ｉ〜Ｉ７ｉ，Ｉ８ｊ
，Ｉ９ｊ，Ｉ１０ｉ〜Ｉ１２ｉ，Ｉ１３ｋ，Ｉ１
４ｋ……インバータ、ＮＯ１，ＮＯ２ｉ〜ＮＯ５
ｉ……ノア回路、ＮＡ１，ＮＡ２ｊ，ＮＡ３ｋ…
…ナンド回路。

Claims (1)

    【実用新案登録請求の範囲】
  1. 書込み回路、Ｘデコーダ、Ｙデコーダの出力を
    、第１の制御信号が加えられると、全デイジツト
    線を非選択状態にし、全ワード線を書込み電圧に
    引き上げるような出力に、また、第２の制御信号
    が加えられると、全ワード線を非選択状態にし、
    全デイジツト線を書込み電圧に引き上げるような
    出力にする手段を備えたことを特徴とするテスト
    回路内蔵ＥＰＲＯＭ。
JP1985052285U 1985-04-09 1985-04-09 Expired - Lifetime JPH051040Y2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP1985052285U JPH051040Y2 (ja) 1985-04-09 1985-04-09
US06/849,630 US4870618A (en) 1985-04-09 1986-04-09 Semiconductor memory equipped with test circuit for testing data holding characteristic during data programming period

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1985052285U JPH051040Y2 (ja) 1985-04-09 1985-04-09

Publications (2)

Publication Number Publication Date
JPS61170200U true JPS61170200U (ja) 1986-10-22
JPH051040Y2 JPH051040Y2 (ja) 1993-01-12

Family

ID=12910524

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1985052285U Expired - Lifetime JPH051040Y2 (ja) 1985-04-09 1985-04-09

Country Status (2)

Country Link
US (1) US4870618A (ja)
JP (1) JPH051040Y2 (ja)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5197033A (en) 1986-07-18 1993-03-23 Hitachi, Ltd. Semiconductor device incorporating internal power supply for compensating for deviation in operating condition and fabrication process conditions
JPH0766675B2 (ja) * 1987-07-14 1995-07-19 株式会社東芝 プログラマブルｒｏｍ
JPH02177100A (ja) * 1988-12-27 1990-07-10 Nec Corp 半導体記憶装置のテスト回路
DE69034227T2 (de) * 1989-04-13 2007-05-03 Sandisk Corp., Sunnyvale EEprom-System mit Blocklöschung
US5172338B1 (en) * 1989-04-13 1997-07-08 Sandisk Corp Multi-state eeprom read and write circuits and techniques
US7447069B1 (en) 1989-04-13 2008-11-04 Sandisk Corporation Flash EEprom system
EP0432481A3 (en) * 1989-12-14 1992-04-29 Texas Instruments Incorporated Methods and apparatus for verifying the state of a plurality of electrically programmable memory cells
WO1992006475A1 (en) * 1990-10-02 1992-04-16 Kabushiki Kaisha Toshiba Semiconductor memory
US5148436A (en) * 1990-10-15 1992-09-15 Motorola, Inc. Circuit for detecting false read data from eprom
JPH04188498A (ja) * 1990-11-22 1992-07-07 Fujitsu Ltd 書き換え可能な不揮発性半導体記憶装置
JP2829134B2 (ja) * 1990-12-27 1998-11-25 株式会社東芝 半導体記憶装置
JP3526894B2 (ja) * 1993-01-12 2004-05-17 株式会社ルネサステクノロジ 不揮発性半導体記憶装置
JP2001006379A (ja) * 1999-06-16 2001-01-12 Fujitsu Ltd 複写、移動機能を有するフラッシュメモリ
US6574158B1 (en) 2001-09-27 2003-06-03 Cypress Semiconductor Corp. Method and system for measuring threshold of EPROM cells
KR100515055B1 (ko) * 2002-12-12 2005-09-14 삼성전자주식회사 모든 칼럼 선택 트랜지스터들을 선택할 수 있는 칼럼 프리디코더를 갖는 플레쉬 메모리 장치와 그 스트레스 테스트방법

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5936400A (ja) * 1982-07-19 1984-02-28 モトロ−ラ・インコ−ポレ−テツド 半導体メモリアレ−検査方法
JPS59146495A (ja) * 1983-02-10 1984-08-22 Fujitsu Ltd 半導体記憶装置

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58222489A (ja) * 1982-06-18 1983-12-24 Nec Corp 半導体記憶装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5936400A (ja) * 1982-07-19 1984-02-28 モトロ−ラ・インコ−ポレ−テツド 半導体メモリアレ−検査方法
JPS59146495A (ja) * 1983-02-10 1984-08-22 Fujitsu Ltd 半導体記憶装置

Also Published As

Publication number Publication date
US4870618A (en) 1989-09-26
JPH051040Y2 (ja) 1993-01-12

Similar Documents

Publication Publication Date Title
JPS61170200U (ja)
JPH0770212B2 (ja) 半導体メモリ回路
JPH04119597A (ja) 不揮発性半導体記憶装置のセンスアンプ
US5574695A (en) Semiconductor memory device with bit line load circuit for high speed operation
KR100443910B1 (ko) 반도체 메모리 장치 및 이 장치의 메모리 셀 억세스 방법
JPS6223397B2 (ja)
JPS599990B2 (ja) 半導体記憶装置
JP2621411B2 (ja) 不揮発性半導体記憶装置
JPH01264692A (ja) 半導体メモリ回路
JPH09120674A (ja) 半導体記憶装置
JPH06105550B2 (ja) 半導体記憶装置
JPH0197498U (ja)
JPH03276758A (ja) ダイナミック型ランダムアクセスメモリ
JPS6448800U (ja)
US5544112A (en) Word line driver circuit
JPS58114596U (ja) 半導体メモリ装置
JPH02285584A (ja) 半導体記憶回路装置
JP2679374B2 (ja) シリアル・アクセス・メモリ
JPS62154286A (ja) 書き替え可能メモリに対するライト・アクセス方式
JPS62150800U (ja)
JPH0713847B2 (ja) 半導体記憶装置
JPS6348694A (ja) 半導体メモリ
JPH0222469B2 (ja)
JPH065078A (ja) 半導体記憶装置
JPS61136396U (ja)