JPS61125039A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法

Info

Publication number
JPS61125039A
JPS61125039A JP59246605A JP24660584A JPS61125039A JP S61125039 A JPS61125039 A JP S61125039A JP 59246605 A JP59246605 A JP 59246605A JP 24660584 A JP24660584 A JP 24660584A JP S61125039 A JPS61125039 A JP S61125039A
Authority
JP
Japan
Prior art keywords
nitride film
substrate
epitaxial layer
grown
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59246605A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0478178B2 (https=
Inventor
Yukio Minato
湊　幸男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP59246605A priority Critical patent/JPS61125039A/ja
Priority to US06/800,257 priority patent/US4692996A/en
Publication of JPS61125039A publication Critical patent/JPS61125039A/ja
Publication of JPH0478178B2 publication Critical patent/JPH0478178B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/021—Manufacture or treatment of air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/061—Manufacture or treatment using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/20—Air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]

Landscapes

  • Element Separation (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
JP59246605A 1984-11-21 1984-11-21 半導体装置の製造方法 Granted JPS61125039A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP59246605A JPS61125039A (ja) 1984-11-21 1984-11-21 半導体装置の製造方法
US06/800,257 US4692996A (en) 1984-11-21 1985-11-21 Method of fabricating semiconductor devices in dielectrically isolated silicon islands

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59246605A JPS61125039A (ja) 1984-11-21 1984-11-21 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JPS61125039A true JPS61125039A (ja) 1986-06-12
JPH0478178B2 JPH0478178B2 (https=) 1992-12-10

Family

ID=17150892

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59246605A Granted JPS61125039A (ja) 1984-11-21 1984-11-21 半導体装置の製造方法

Country Status (2)

Country Link
US (1) US4692996A (https=)
JP (1) JPS61125039A (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0529772U (ja) * 1991-09-30 1993-04-20 日章株式会社 香り付き印肉

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4863562A (en) * 1988-02-11 1989-09-05 Sgs-Thomson Microelectronics, Inc. Method for forming a non-planar structure on the surface of a semiconductor substrate
TW309647B (https=) * 1995-12-30 1997-07-01 Hyundai Electronics Ind
US5963817A (en) * 1997-10-16 1999-10-05 International Business Machines Corporation Bulk and strained silicon on insulator using local selective oxidation
DE102008052172B4 (de) * 2008-10-17 2014-01-23 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Vorrichtung zum Erzeugen eines Korrektursignals
US7851790B2 (en) * 2008-12-30 2010-12-14 Intel Corporation Isolated Germanium nanowire on Silicon fin

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5612749A (en) * 1979-07-12 1981-02-07 Matsushita Electric Ind Co Ltd Production of semiconductor device
JPS5768048A (en) * 1980-10-16 1982-04-26 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device and manufacture thereof
JPS57157569A (en) * 1981-03-02 1982-09-29 Rockwell International Corp N-p-n lateral transistor array of submicron size and method of forming same
JPS58175844A (ja) * 1982-04-08 1983-10-15 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
JPS58192345A (ja) * 1982-05-07 1983-11-09 Nippon Telegr & Teleph Corp <Ntt> 半導体装置の製造方法
JPS59202648A (ja) * 1983-05-02 1984-11-16 Oki Electric Ind Co Ltd 半導体装置の製造方法
JPS6094738A (ja) * 1983-10-28 1985-05-27 Matsushita Electric Works Ltd 半導体基板

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4373252A (en) * 1981-02-17 1983-02-15 Fairchild Camera & Instrument Method for manufacturing a semiconductor structure having reduced lateral spacing between buried regions
US4580331A (en) * 1981-07-01 1986-04-08 Rockwell International Corporation PNP-type lateral transistor with minimal substrate operation interference and method for producing same
US4502913A (en) * 1982-06-30 1985-03-05 International Business Machines Corporation Total dielectric isolation for integrated circuits
FR2554638A1 (fr) * 1983-11-04 1985-05-10 Efcis Procede de fabrication de structures integrees de silicium sur ilots isoles du substrat

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5612749A (en) * 1979-07-12 1981-02-07 Matsushita Electric Ind Co Ltd Production of semiconductor device
JPS5768048A (en) * 1980-10-16 1982-04-26 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device and manufacture thereof
JPS57157569A (en) * 1981-03-02 1982-09-29 Rockwell International Corp N-p-n lateral transistor array of submicron size and method of forming same
JPS58175844A (ja) * 1982-04-08 1983-10-15 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
JPS58192345A (ja) * 1982-05-07 1983-11-09 Nippon Telegr & Teleph Corp <Ntt> 半導体装置の製造方法
JPS59202648A (ja) * 1983-05-02 1984-11-16 Oki Electric Ind Co Ltd 半導体装置の製造方法
JPS6094738A (ja) * 1983-10-28 1985-05-27 Matsushita Electric Works Ltd 半導体基板

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0529772U (ja) * 1991-09-30 1993-04-20 日章株式会社 香り付き印肉

Also Published As

Publication number Publication date
US4692996A (en) 1987-09-15
JPH0478178B2 (https=) 1992-12-10

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