JPS6112301B2 - - Google Patents

Info

Publication number
JPS6112301B2
JPS6112301B2 JP19345381A JP19345381A JPS6112301B2 JP S6112301 B2 JPS6112301 B2 JP S6112301B2 JP 19345381 A JP19345381 A JP 19345381A JP 19345381 A JP19345381 A JP 19345381A JP S6112301 B2 JPS6112301 B2 JP S6112301B2
Authority
JP
Japan
Prior art keywords
signal
service
flop
flip
becomes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP19345381A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5896328A (ja
Inventor
Minoru Nishino
Yoshito Hagiwara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP19345381A priority Critical patent/JPS5896328A/ja
Publication of JPS5896328A publication Critical patent/JPS5896328A/ja
Publication of JPS6112301B2 publication Critical patent/JPS6112301B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
JP19345381A 1981-12-01 1981-12-01 入出力制御装置 Granted JPS5896328A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19345381A JPS5896328A (ja) 1981-12-01 1981-12-01 入出力制御装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19345381A JPS5896328A (ja) 1981-12-01 1981-12-01 入出力制御装置

Publications (2)

Publication Number Publication Date
JPS5896328A JPS5896328A (ja) 1983-06-08
JPS6112301B2 true JPS6112301B2 (enExample) 1986-04-07

Family

ID=16308242

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19345381A Granted JPS5896328A (ja) 1981-12-01 1981-12-01 入出力制御装置

Country Status (1)

Country Link
JP (1) JPS5896328A (enExample)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62119654A (ja) * 1985-11-20 1987-05-30 Fujitsu Ltd チヤネルビジ−制御方式

Also Published As

Publication number Publication date
JPS5896328A (ja) 1983-06-08

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