JPS5896328A - 入出力制御装置 - Google Patents

入出力制御装置

Info

Publication number
JPS5896328A
JPS5896328A JP19345381A JP19345381A JPS5896328A JP S5896328 A JPS5896328 A JP S5896328A JP 19345381 A JP19345381 A JP 19345381A JP 19345381 A JP19345381 A JP 19345381A JP S5896328 A JPS5896328 A JP S5896328A
Authority
JP
Japan
Prior art keywords
signal
flip
flop
data transfer
signal line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP19345381A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6112301B2 (enExample
Inventor
Minoru Nishino
西野　實
Yoshito Hagiwara
萩原　義人
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP19345381A priority Critical patent/JPS5896328A/ja
Publication of JPS5896328A publication Critical patent/JPS5896328A/ja
Publication of JPS6112301B2 publication Critical patent/JPS6112301B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
JP19345381A 1981-12-01 1981-12-01 入出力制御装置 Granted JPS5896328A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19345381A JPS5896328A (ja) 1981-12-01 1981-12-01 入出力制御装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19345381A JPS5896328A (ja) 1981-12-01 1981-12-01 入出力制御装置

Publications (2)

Publication Number Publication Date
JPS5896328A true JPS5896328A (ja) 1983-06-08
JPS6112301B2 JPS6112301B2 (enExample) 1986-04-07

Family

ID=16308242

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19345381A Granted JPS5896328A (ja) 1981-12-01 1981-12-01 入出力制御装置

Country Status (1)

Country Link
JP (1) JPS5896328A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62119654A (ja) * 1985-11-20 1987-05-30 Fujitsu Ltd チヤネルビジ−制御方式

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62119654A (ja) * 1985-11-20 1987-05-30 Fujitsu Ltd チヤネルビジ−制御方式

Also Published As

Publication number Publication date
JPS6112301B2 (enExample) 1986-04-07

Similar Documents

Publication Publication Date Title
US5388216A (en) Circuit for controlling generation of an acknowledge signal and a busy signal in a centronics compatible parallel interface
CA1145003A (en) Computer channel access circuit for multiple input-output devices
US4644462A (en) Input/output interrupt system
US4729090A (en) DMA system employing plural bus request and grant signals for improving bus data transfer speed
JPH01162967A (ja) 割込み処理方法及び装置
US3706974A (en) Interface multiplexer
JPS6112301B2 (enExample)
JPH02170644A (ja) マルチメディア通信システムの優先送信方法
JP2747154B2 (ja) 入出力処理装置
JPH04107663A (ja) 同期式通信システムの制御方式
JPS61250762A (ja) デ−タ転送装置
JPS5953575B2 (ja) 通信制御方式
JPH01205363A (ja) 直接メモリアクセス状態判定回路
JPS595332A (ja) 磁気デイスク・サブシステムにおける割込優先方式
KR20230104625A (ko) Ap 구동형 링크 복구에 대해 대기 시에 모뎀 안정화를 위한 시스템 및 방법
JPH063924B2 (ja) ポーリング制御方法
JPH0682348B2 (ja) 入出力制御方式
JPS59123027A (ja) 転送要求処理方式
JPS59161721A (ja) チヤネル装置
JPS6324438A (ja) デ−タ転送制御装置
JPS62191954A (ja) 通信制御装置
JPH0240755A (ja) データ処理装置
JPH01214940A (ja) 割込み制御方法
JPS59119430A (ja) 入出力制御装置
JPH01233544A (ja) データ転送方式