JPS6111873A - １６ビツトマイクロプロセツサによる８ビツトおよび１６ビツトの各周辺装置へのアクセス方法 - Google Patents

１６ビツトマイクロプロセツサによる８ビツトおよび１６ビツトの各周辺装置へのアクセス方法

Info

Publication number
JPS6111873A
JPS6111873A JP13203584A JP13203584A JPS6111873A JP S6111873 A JPS6111873 A JP S6111873A JP 13203584 A JP13203584 A JP 13203584A JP 13203584 A JP13203584 A JP 13203584A JP S6111873 A JPS6111873 A JP S6111873A
Authority
JP
Japan
Prior art keywords
bit
mpu
address
data
peripheral device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13203584A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0140366B2 (enrdf_load_stackoverflow
Inventor
Takeshi Matoba
的場　武
Kazuhiro Kamei
亀井　和宏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kokusai Denki Electric Inc
Original Assignee
Kokusai Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kokusai Electric Co Ltd filed Critical Kokusai Electric Co Ltd
Priority to JP13203584A priority Critical patent/JPS6111873A/ja
Publication of JPS6111873A publication Critical patent/JPS6111873A/ja
Publication of JPH0140366B2 publication Critical patent/JPH0140366B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4009—Coupling between buses with data restructuring
    • G06F13/4018—Coupling between buses with data restructuring with data-width conversion

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bus Control (AREA)
JP13203584A 1984-06-28 1984-06-28 １６ビツトマイクロプロセツサによる８ビツトおよび１６ビツトの各周辺装置へのアクセス方法 Granted JPS6111873A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13203584A JPS6111873A (ja) 1984-06-28 1984-06-28 １６ビツトマイクロプロセツサによる８ビツトおよび１６ビツトの各周辺装置へのアクセス方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13203584A JPS6111873A (ja) 1984-06-28 1984-06-28 １６ビツトマイクロプロセツサによる８ビツトおよび１６ビツトの各周辺装置へのアクセス方法

Publications (2)

Publication Number Publication Date
JPS6111873A true JPS6111873A (ja) 1986-01-20
JPH0140366B2 JPH0140366B2 (enrdf_load_stackoverflow) 1989-08-28

Family

ID=15071975

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13203584A Granted JPS6111873A (ja) 1984-06-28 1984-06-28 １６ビツトマイクロプロセツサによる８ビツトおよび１６ビツトの各周辺装置へのアクセス方法

Country Status (1)

Country Link
JP (1) JPS6111873A (enrdf_load_stackoverflow)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61156358A (ja) * 1984-12-10 1986-07-16 イング・チイ・オリベツチ・アンド・チイ・エス・ピー・ア バスコンバータ
JPS6329870A (ja) * 1986-07-23 1988-02-08 Seiko Epson Corp デバイス装置のアクセス制御回路
JPS63156234A (ja) * 1986-12-19 1988-06-29 Fujitsu Ltd マイクロプロセツサの動作方式
JPS6459447A (en) * 1987-08-31 1989-03-07 Hitachi Ltd Data transfer circuit
JPH01116859A (ja) * 1987-10-30 1989-05-09 Matsushita Electric Ind Co Ltd バス制御装置
JPH0239345A (ja) * 1988-07-29 1990-02-08 Nec Eng Ltd Ｌｓｉ化バス制御回路
JPH02113359A (ja) * 1988-10-22 1990-04-25 Nec Corp Ｃｐｕシステムのバス回路
US6032246A (en) * 1997-09-19 2000-02-29 Mitsubishi Denki Kabushiki Kaisha Bit-slice processing unit having M CPU's reading an N-bit width data element stored bit-sliced across M memories
JP2011512599A (ja) * 2008-02-15 2011-04-21 フリースケール セミコンダクター インコーポレイテッド 周辺装置モジュールレジスタアクセス方法及び装置

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5991560A (ja) * 1982-11-18 1984-05-26 Toshiba Corp マイクロプロセツサ

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5991560A (ja) * 1982-11-18 1984-05-26 Toshiba Corp マイクロプロセツサ

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61156358A (ja) * 1984-12-10 1986-07-16 イング・チイ・オリベツチ・アンド・チイ・エス・ピー・ア バスコンバータ
JPS6329870A (ja) * 1986-07-23 1988-02-08 Seiko Epson Corp デバイス装置のアクセス制御回路
JPS63156234A (ja) * 1986-12-19 1988-06-29 Fujitsu Ltd マイクロプロセツサの動作方式
JPS6459447A (en) * 1987-08-31 1989-03-07 Hitachi Ltd Data transfer circuit
JPH01116859A (ja) * 1987-10-30 1989-05-09 Matsushita Electric Ind Co Ltd バス制御装置
JPH0239345A (ja) * 1988-07-29 1990-02-08 Nec Eng Ltd Ｌｓｉ化バス制御回路
JPH02113359A (ja) * 1988-10-22 1990-04-25 Nec Corp Ｃｐｕシステムのバス回路
US6032246A (en) * 1997-09-19 2000-02-29 Mitsubishi Denki Kabushiki Kaisha Bit-slice processing unit having M CPU's reading an N-bit width data element stored bit-sliced across M memories
JP2011512599A (ja) * 2008-02-15 2011-04-21 フリースケール セミコンダクター インコーポレイテッド 周辺装置モジュールレジスタアクセス方法及び装置
US8977790B2 (en) 2008-02-15 2015-03-10 Freescale Semiconductor, Inc. Peripheral module register access methods and apparatus

Also Published As

Publication number Publication date
JPH0140366B2 (enrdf_load_stackoverflow) 1989-08-28

Similar Documents

Publication Publication Date Title
EP0120889B1 (en) Direct memory access peripheral unit controller
KR900004006B1 (ko) 마이크로 프로세서 시스템
EP0189638B1 (en) Bus width adapter
KR900007564B1 (ko) 동적 버스를 갖는 데이터 처리기
US6070204A (en) Method and apparatus for using universal serial bus keyboard to control DOS operations
US4607328A (en) Data transfer apparatus for a microcomputer system
JPS6111873A (ja) １６ビツトマイクロプロセツサによる８ビツトおよび１６ビツトの各周辺装置へのアクセス方法
EP0321775B1 (en) Secure data processing system using commodity devices
US20030217218A1 (en) Interface for devices having different data bus widths and data transfer method using the interface
US5748920A (en) Transaction queue in a graphics controller chip
JPS61251950A (ja) インタ−フエイス装置
US5715411A (en) Apparatus and method of converting subtractive decode device cycles to positive peripheral component interface decode device cycles
KR960001023B1 (ko) 이기종 버스시스템에서의 버스 공유방법 및 버스 스와핑장치
JP3480961B2 (ja) メモリアクセス方法
JP2586134B2 (ja) Ｃｐｕ外部バスアクセス方法
JPS603049A (ja) バスインタ−フエ−ス装置
EP0439594B1 (en) Device for interfacing a main processor bus connected to a main processor to a peripheral bus having a number of peripheral devices connected thereto
JP2976443B2 (ja) システムバスを介してデータをやりとりする情報処理装置
JPH05250310A (ja) データ処理装置
JP3304107B2 (ja) データバスの制御方式
JP3242474B2 (ja) データ処理装置
JPH04112251A (ja) マイクロコンピュータ
JPS6266333A (ja) 間接アドレスレジスタ制御方式
JPH04333954A (ja) 情報処理装置
JPH05143718A (ja) 画像処理装置

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees