JPS61117654A - プロセツサ間の情報転送同期方式 - Google Patents

プロセツサ間の情報転送同期方式

Info

Publication number
JPS61117654A
JPS61117654A JP59239241A JP23924184A JPS61117654A JP S61117654 A JPS61117654 A JP S61117654A JP 59239241 A JP59239241 A JP 59239241A JP 23924184 A JP23924184 A JP 23924184A JP S61117654 A JPS61117654 A JP S61117654A
Authority
JP
Japan
Prior art keywords
processors
data
transfer
data transfer
signal line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59239241A
Other languages
English (en)
Japanese (ja)
Other versions
JPH027099B2 (enExample
Inventor
Fumiaki Ishino
文明 石野
Yoshitaka Ito
芳孝 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NTT Inc
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP59239241A priority Critical patent/JPS61117654A/ja
Publication of JPS61117654A publication Critical patent/JPS61117654A/ja
Publication of JPH027099B2 publication Critical patent/JPH027099B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Multi Processors (AREA)
JP59239241A 1984-11-13 1984-11-13 プロセツサ間の情報転送同期方式 Granted JPS61117654A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59239241A JPS61117654A (ja) 1984-11-13 1984-11-13 プロセツサ間の情報転送同期方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59239241A JPS61117654A (ja) 1984-11-13 1984-11-13 プロセツサ間の情報転送同期方式

Publications (2)

Publication Number Publication Date
JPS61117654A true JPS61117654A (ja) 1986-06-05
JPH027099B2 JPH027099B2 (enExample) 1990-02-15

Family

ID=17041837

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59239241A Granted JPS61117654A (ja) 1984-11-13 1984-11-13 プロセツサ間の情報転送同期方式

Country Status (1)

Country Link
JP (1) JPS61117654A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0223480A (ja) * 1988-07-13 1990-01-25 Agency Of Ind Science & Technol 並列演算装置

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55917A (en) * 1978-06-16 1980-01-07 Japanese National Railways<Jnr> Multiple synchronous operation system
JPS5829032A (ja) * 1981-08-14 1983-02-21 Hitachi Ltd デ−タ転送方式

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55917A (en) * 1978-06-16 1980-01-07 Japanese National Railways<Jnr> Multiple synchronous operation system
JPS5829032A (ja) * 1981-08-14 1983-02-21 Hitachi Ltd デ−タ転送方式

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0223480A (ja) * 1988-07-13 1990-01-25 Agency Of Ind Science & Technol 並列演算装置

Also Published As

Publication number Publication date
JPH027099B2 (enExample) 1990-02-15

Similar Documents

Publication Publication Date Title
US4615017A (en) Memory controller with synchronous or asynchronous interface
US3323109A (en) Multiple computer-multiple memory system
US5438665A (en) Direct memory access controller for handling cyclic execution of data transfer in accordance with stored transfer control information
JPS6345670A (ja) プロセツサ間同期装置
US6157971A (en) Source-destination re-timed cooperative communication bus
EP0939374A2 (en) Processor for information processing equipment and control method
JPS61117654A (ja) プロセツサ間の情報転送同期方式
GB2181578A (en) Clock delay for microprocessor
JPS6136845A (ja) シングルチツプマイクロコンピユ−タ
JPH04323755A (ja) Ｄｍａ装置
JPH03177953A (ja) データ転送方式
JPS5983235A (ja) プロセツサ間のインタ−フエ−ス方式
JPH0222748A (ja) 不揮発生メモリ制御回路
JP2945668B2 (ja) パイプライン処理装置
JPS6049464A (ja) マルチプロセッサ計算機におけるプロセッサ間通信方式
JPH01259441A (ja) バスインタフエース装置
SU1156080A1 (ru) Двухпортовое устройство сопр жени в вычислительной системе
JPH0426744B2 (enExample)
JP2645462B2 (ja) データ処理システム
JPS5834519Y2 (ja) 信号授受装置
JPS63305406A (ja) プログラマブル・コントロ−ラ
JPS63204322A (ja) 情報処理装置
JPS6213690B2 (enExample)
JPH02211571A (ja) 情報処理装置
JPS61120262A (ja) メモリ間インテリジエントｄｍａ制御装置