JPS55917A - Multiple synchronous operation system - Google Patents

Multiple synchronous operation system

Info

Publication number
JPS55917A
JPS55917A JP7287778A JP7287778A JPS55917A JP S55917 A JPS55917 A JP S55917A JP 7287778 A JP7287778 A JP 7287778A JP 7287778 A JP7287778 A JP 7287778A JP S55917 A JPS55917 A JP S55917A
Authority
JP
Japan
Prior art keywords
freeze
signal
time
cpu
respective systems
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7287778A
Other languages
Japanese (ja)
Other versions
JPS5814692B2 (en
Inventor
Yoji Ono
Chuhei Kamoshita
Shigekazu Asada
Shigeaki Kikuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
JAPANESE NATIONAL RAILWAYS<JNR>
Nippon Signal Co Ltd
Japan National Railways
Original Assignee
JAPANESE NATIONAL RAILWAYS<JNR>
Nippon Signal Co Ltd
Japan National Railways
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by JAPANESE NATIONAL RAILWAYS<JNR>, Nippon Signal Co Ltd, Japan National Railways filed Critical JAPANESE NATIONAL RAILWAYS<JNR>
Priority to JP53072877A priority Critical patent/JPS5814692B2/en
Publication of JPS55917A publication Critical patent/JPS55917A/en
Publication of JPS5814692B2 publication Critical patent/JPS5814692B2/en
Expired legal-status Critical Current

Links

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  • Hardware Redundancy (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE: To accord points in time when specific instructions are executed by halting CPU at every time when the CPU executes a specific instruction, by synchronizing signals which halts CPUs of respective systems, and by releating CPUs of respective systems from the halting state by the synchronizing signal.
CONSTITUTION: On receiving specific instruction execution signal S1from CPU2A, 1st-system freeze circuit 1.1A outputs freeze signal S2 halt CPU2A and also to operate freeze synchronous circuit 1.2A. Once freeze circuits 1.1B and 1.1C of two systems output freeze signal S2 on receiving signal S1 from CPUs 2B and 2C, freeze synchronous circuits 1.2A to 1.2C of respective systems output synchronizing signal S3 to reset freeze circuit 1.1A to 1.1C at the same time, releasing the CPU of each system from the halting state, thereby executing an instruction of the next step. Therefore, even if a difference would occur at the point in time when the specific instruction execution signal is sent from the CPU of each system, points in time of the next steps can be made to agree one another among respective systems.
COPYRIGHT: (C)1980,JPO&Japio
JP53072877A 1978-06-16 1978-06-16 Multiple system synchronous operation method Expired JPS5814692B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53072877A JPS5814692B2 (en) 1978-06-16 1978-06-16 Multiple system synchronous operation method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53072877A JPS5814692B2 (en) 1978-06-16 1978-06-16 Multiple system synchronous operation method

Publications (2)

Publication Number Publication Date
JPS55917A true JPS55917A (en) 1980-01-07
JPS5814692B2 JPS5814692B2 (en) 1983-03-22

Family

ID=13501995

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53072877A Expired JPS5814692B2 (en) 1978-06-16 1978-06-16 Multiple system synchronous operation method

Country Status (1)

Country Link
JP (1) JPS5814692B2 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5876922A (en) * 1981-10-30 1983-05-10 Nec Home Electronics Ltd Simultaneous start system of plural microcomputers
JPS6121562A (en) * 1984-05-31 1986-01-30 ゼネラル・エレクトリツク・カンパニイ Faul allowance synchronizer for multiple processor system
JPS61117654A (en) * 1984-11-13 1986-06-05 Nippon Telegr & Teleph Corp <Ntt> Information transfer synchronizing system between processors
JPS61150061A (en) * 1984-12-25 1986-07-08 Panafacom Ltd Processor linking system
JPS61177566A (en) * 1985-01-30 1986-08-09 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Execution of application service program written in high level program language by multiplex processor/data processing system
JPS62134752A (en) * 1985-12-06 1987-06-17 Nippon Telegr & Teleph Corp <Ntt> Inter-processor synchronizing system

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5361944A (en) * 1976-11-16 1978-06-02 Nippon Telegr & Teleph Corp <Ntt> Debug system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5361944A (en) * 1976-11-16 1978-06-02 Nippon Telegr & Teleph Corp <Ntt> Debug system

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5876922A (en) * 1981-10-30 1983-05-10 Nec Home Electronics Ltd Simultaneous start system of plural microcomputers
JPS6121562A (en) * 1984-05-31 1986-01-30 ゼネラル・エレクトリツク・カンパニイ Faul allowance synchronizer for multiple processor system
JPS61117654A (en) * 1984-11-13 1986-06-05 Nippon Telegr & Teleph Corp <Ntt> Information transfer synchronizing system between processors
JPH027099B2 (en) * 1984-11-13 1990-02-15 Nippon Telegraph & Telephone
JPS61150061A (en) * 1984-12-25 1986-07-08 Panafacom Ltd Processor linking system
JPS61177566A (en) * 1985-01-30 1986-08-09 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Execution of application service program written in high level program language by multiplex processor/data processing system
JPH0223894B2 (en) * 1985-01-30 1990-05-25 Intaanashonaru Bijinesu Mashiinzu Corp
JPS62134752A (en) * 1985-12-06 1987-06-17 Nippon Telegr & Teleph Corp <Ntt> Inter-processor synchronizing system

Also Published As

Publication number Publication date
JPS5814692B2 (en) 1983-03-22

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