JPS5552171A - Busy check circuit of one line type - Google Patents

Busy check circuit of one line type

Info

Publication number
JPS5552171A
JPS5552171A JP12558778A JP12558778A JPS5552171A JP S5552171 A JPS5552171 A JP S5552171A JP 12558778 A JP12558778 A JP 12558778A JP 12558778 A JP12558778 A JP 12558778A JP S5552171 A JPS5552171 A JP S5552171A
Authority
JP
Japan
Prior art keywords
busy
instruction
processors
register
line type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12558778A
Other languages
Japanese (ja)
Other versions
JPS6126110B2 (en
Inventor
Tetsuo Yonezawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP12558778A priority Critical patent/JPS5552171A/en
Publication of JPS5552171A publication Critical patent/JPS5552171A/en
Publication of JPS6126110B2 publication Critical patent/JPS6126110B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Debugging And Monitoring (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE: To simplify the circuit constitution, by wiring together the common control line tying a plurality of processors having control function.
CONSTITUTION: The inverting signal of BUSY output from the processors of P1 to P11 is tied with one line L. When request signal is given from the processor P1, it executes IN11 instruction, BUSY state is inputted from the register 101, and if BUSY="0", the reset set type register 102 is set with OUT11 instruction, and the output Q is equal to "1". After required processing, P1 resets the register 102 with OUT12 instruction and initial state is returned with Q="0". Next, if the request from a plurality of processors is duplicated, P2WPn-1 execute IN×2 instruction in order, but since BUSY="0", BUSY of the processor itself is released with OUT×2 instruction. Pn inputs BOSY="1" and enters required processing.
COPYRIGHT: (C)1980,JPO&Japio
JP12558778A 1978-10-11 1978-10-11 Busy check circuit of one line type Granted JPS5552171A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12558778A JPS5552171A (en) 1978-10-11 1978-10-11 Busy check circuit of one line type

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12558778A JPS5552171A (en) 1978-10-11 1978-10-11 Busy check circuit of one line type

Publications (2)

Publication Number Publication Date
JPS5552171A true JPS5552171A (en) 1980-04-16
JPS6126110B2 JPS6126110B2 (en) 1986-06-19

Family

ID=14913859

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12558778A Granted JPS5552171A (en) 1978-10-11 1978-10-11 Busy check circuit of one line type

Country Status (1)

Country Link
JP (1) JPS5552171A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6225355A (en) * 1985-07-26 1987-02-03 Hitachi Ltd Method for propagating signal between integrated circuits
JPH01120601A (en) * 1987-11-05 1989-05-12 Honda Motor Co Ltd Controller using two central processing unit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6225355A (en) * 1985-07-26 1987-02-03 Hitachi Ltd Method for propagating signal between integrated circuits
JPH01120601A (en) * 1987-11-05 1989-05-12 Honda Motor Co Ltd Controller using two central processing unit

Also Published As

Publication number Publication date
JPS6126110B2 (en) 1986-06-19

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