JPS61111561A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS61111561A
JPS61111561A JP59209238A JP20923884A JPS61111561A JP S61111561 A JPS61111561 A JP S61111561A JP 59209238 A JP59209238 A JP 59209238A JP 20923884 A JP20923884 A JP 20923884A JP S61111561 A JPS61111561 A JP S61111561A
Authority
JP
Japan
Prior art keywords
chip
pads
contact film
contact
wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59209238A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0577184B2 (https=
Inventor
Satoru Tanizawa
谷澤　哲
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP59209238A priority Critical patent/JPS61111561A/ja
Priority to US06/784,439 priority patent/US4721995A/en
Priority to DE8585401948T priority patent/DE3571535D1/de
Priority to EP85401948A priority patent/EP0178227B1/en
Publication of JPS61111561A publication Critical patent/JPS61111561A/ja
Publication of JPH0577184B2 publication Critical patent/JPH0577184B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/688—Flexible insulating substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Design And Manufacture Of Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
JP59209238A 1984-10-05 1984-10-05 半導体装置 Granted JPS61111561A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP59209238A JPS61111561A (ja) 1984-10-05 1984-10-05 半導体装置
US06/784,439 US4721995A (en) 1984-10-05 1985-10-04 Integrated circuit semiconductor device formed on a wafer
DE8585401948T DE3571535D1 (en) 1984-10-05 1985-10-04 Integrated circuit semiconductor device formed on a wafer
EP85401948A EP0178227B1 (en) 1984-10-05 1985-10-04 Integrated circuit semiconductor device formed on a wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59209238A JPS61111561A (ja) 1984-10-05 1984-10-05 半導体装置

Publications (2)

Publication Number Publication Date
JPS61111561A true JPS61111561A (ja) 1986-05-29
JPH0577184B2 JPH0577184B2 (https=) 1993-10-26

Family

ID=16569645

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59209238A Granted JPS61111561A (ja) 1984-10-05 1984-10-05 半導体装置

Country Status (4)

Country Link
US (1) US4721995A (https=)
EP (1) EP0178227B1 (https=)
JP (1) JPS61111561A (https=)
DE (1) DE3571535D1 (https=)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01500944A (ja) * 1986-09-26 1989-03-30 ゼネラル・エレクトリック・カンパニイ 多重チップ集積回路パッケージ、集積回路チップのパッケージ及び集積回路チップをパッケージする方法
JP2018531504A (ja) * 2015-09-02 2018-10-25 オキュラス ブイアール，エルエルシー 半導体デバイスの組立
US10916192B2 (en) 2016-04-26 2021-02-09 Facebook Technologies, Llc Display with redundant light emitting devices

Families Citing this family (63)

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EP0305398B1 (en) * 1986-05-01 1991-09-25 Honeywell Inc. Multiple integrated circuit interconnection arrangement
US4937203A (en) * 1986-09-26 1990-06-26 General Electric Company Method and configuration for testing electronic circuits and integrated circuit chips using a removable overlay layer
US4884122A (en) * 1988-08-05 1989-11-28 General Electric Company Method and configuration for testing electronic circuits and integrated circuit chips using a removable overlay layer
US5094709A (en) * 1986-09-26 1992-03-10 General Electric Company Apparatus for packaging integrated circuit chips employing a polymer film overlay layer
US4866508A (en) * 1986-09-26 1989-09-12 General Electric Company Integrated circuit packaging configuration for rapid customized design and unique test capability
EP0286660B1 (en) * 1986-09-26 1992-03-04 General Electric Company Method and configuration for testing electronic circuits and integrated circuit chips using a removable overlay layer
JPS63131561A (ja) * 1986-11-18 1988-06-03 インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン 電子パツケージ
US4835704A (en) * 1986-12-29 1989-05-30 General Electric Company Adaptive lithography system to provide high density interconnect
US5191224A (en) * 1987-04-22 1993-03-02 Hitachi, Ltd. Wafer scale of full wafer memory system, packaging method thereof, and wafer processing method employed therein
US4933810A (en) * 1987-04-30 1990-06-12 Honeywell Inc. Integrated circuit interconnector
US5089881A (en) * 1988-11-03 1992-02-18 Micro Substrates, Inc. Fine-pitch chip carrier
US5038201A (en) * 1988-11-08 1991-08-06 Westinghouse Electric Corp. Wafer scale integrated circuit apparatus
DE68929282T2 (de) * 1988-11-09 2001-06-07 Nitto Denko Corp., Ibaraki Leitersubstrat, Filmträger, Halbleiteranordnung mit dem Filmträger und Montagestruktur mit der Halbleiteranordnung
JPH02174255A (ja) * 1988-12-27 1990-07-05 Mitsubishi Electric Corp 半導体集積回路装置
US5349219A (en) * 1989-06-15 1994-09-20 Fujitsu Limited Wafer-scale semiconductor integrated circuit device and method of forming interconnection lines arranged between chips of wafer-scale semiconductor integrated circuit device
JPH04503431A (ja) * 1989-07-03 1992-06-18 ゼネラル・エレクトリック・カンパニイ 力の強い環境内に配置される電子装置
US5231304A (en) * 1989-07-27 1993-07-27 Grumman Aerospace Corporation Framed chip hybrid stacked layer assembly
GB8918482D0 (en) * 1989-08-14 1989-09-20 Inmos Ltd Packaging semiconductor chips
US5239191A (en) * 1990-01-19 1993-08-24 Kabushiki Kaisha Toshiba Semiconductor wafer
US5157255A (en) * 1990-04-05 1992-10-20 General Electric Company Compact, thermally efficient focal plane array and testing and repair thereof
US5146303A (en) * 1990-04-05 1992-09-08 General Electric Company Compact, thermally efficient focal plane array and testing and repair thereof
US5237203A (en) * 1991-05-03 1993-08-17 Trw Inc. Multilayer overlay interconnect for high-density packaging of circuit elements
JP2715810B2 (ja) * 1991-07-25 1998-02-18 日本電気株式会社 フィルムキャリア半導体装置とその製造方法
US5184284A (en) * 1991-09-03 1993-02-02 International Business Machines Corporation Method and apparatus for implementing engineering changes for integrated circuit module
US5239448A (en) * 1991-10-28 1993-08-24 International Business Machines Corporation Formulation of multichip modules
US5355019A (en) * 1992-03-04 1994-10-11 At&T Bell Laboratories Devices with tape automated bonding
JPH06151685A (ja) * 1992-11-04 1994-05-31 Mitsubishi Electric Corp Ｍｃｐ半導体装置
US5703405A (en) * 1993-03-15 1997-12-30 Motorola, Inc. Integrated circuit chip formed from processing two opposing surfaces of a wafer
JPH07169872A (ja) * 1993-12-13 1995-07-04 Fujitsu Ltd 半導体装置及びその製造方法
US6222212B1 (en) 1994-01-27 2001-04-24 Integrated Device Technology, Inc. Semiconductor device having programmable interconnect layers
US5766972A (en) * 1994-06-02 1998-06-16 Mitsubishi Denki Kabushiki Kaisha Method of making resin encapsulated semiconductor device with bump electrodes
US5891761A (en) * 1994-06-23 1999-04-06 Cubic Memory, Inc. Method for forming vertical interconnect process for silicon segments with thermally conductive epoxy preform
US6486528B1 (en) 1994-06-23 2002-11-26 Vertical Circuits, Inc. Silicon segment programming apparatus and three terminal fuse configuration
US6080596A (en) * 1994-06-23 2000-06-27 Cubic Memory Inc. Method for forming vertical interconnect process for silicon segments with dielectric isolation
US5657206A (en) * 1994-06-23 1997-08-12 Cubic Memory, Inc. Conductive epoxy flip-chip package and method
US6255726B1 (en) 1994-06-23 2001-07-03 Cubic Memory, Inc. Vertical interconnect process for silicon segments with dielectric isolation
US6124633A (en) * 1994-06-23 2000-09-26 Cubic Memory Vertical interconnect process for silicon segments with thermally conductive epoxy preform
US5698895A (en) 1994-06-23 1997-12-16 Cubic Memory, Inc. Silicon segment programming method and apparatus
US5675180A (en) * 1994-06-23 1997-10-07 Cubic Memory, Inc. Vertical interconnect process for silicon segments
US6117694A (en) * 1994-07-07 2000-09-12 Tessera, Inc. Flexible lead structures and methods of making same
US5688716A (en) 1994-07-07 1997-11-18 Tessera, Inc. Fan-out semiconductor chip assembly
US6828668B2 (en) * 1994-07-07 2004-12-07 Tessera, Inc. Flexible lead structures and methods of making same
US5518964A (en) * 1994-07-07 1996-05-21 Tessera, Inc. Microelectronic mounting with multiple lead deformation and bonding
US5830782A (en) * 1994-07-07 1998-11-03 Tessera, Inc. Microelectronic element bonding with deformation of leads in rows
US6848173B2 (en) * 1994-07-07 2005-02-01 Tessera, Inc. Microelectric packages having deformed bonded leads and methods therefor
US6429112B1 (en) 1994-07-07 2002-08-06 Tessera, Inc. Multi-layer substrates and fabrication processes
US5798286A (en) * 1995-09-22 1998-08-25 Tessera, Inc. Connecting multiple microelectronic elements with lead deformation
US5666003A (en) * 1994-10-24 1997-09-09 Rohm Co. Ltd. Packaged semiconductor device incorporating heat sink plate
US5639683A (en) * 1994-12-01 1997-06-17 Motorola, Inc. Structure and method for intergrating microwave components on a substrate
JPH08288424A (ja) * 1995-04-18 1996-11-01 Nec Corp 半導体装置
US5653019A (en) * 1995-08-31 1997-08-05 Regents Of The University Of California Repairable chip bonding/interconnect process
RU2133067C1 (ru) * 1996-02-20 1999-07-10 Завьялов Дмитрий Валентинович Интегральная схема
US6667560B2 (en) 1996-05-29 2003-12-23 Texas Instruments Incorporated Board on chip ball grid array
US5936311A (en) * 1996-12-31 1999-08-10 Intel Corporation Integrated circuit alignment marks distributed throughout a surface metal line
US6040624A (en) * 1997-10-02 2000-03-21 Motorola, Inc. Semiconductor device package and method
US6084306A (en) * 1998-05-29 2000-07-04 Texas Instruments Incorporated Bridging method of interconnects for integrated circuit packages
US6300679B1 (en) * 1998-06-01 2001-10-09 Semiconductor Components Industries, Llc Flexible substrate for packaging a semiconductor component
JP2001165998A (ja) * 1999-12-10 2001-06-22 Mitsubishi Electric Corp 半導体モジュール
EP1215725A3 (de) * 2000-12-18 2005-03-23 cubit electronics Gmbh Anordnung zur Aufnahme elektrischer Bauteile und kontaktloser Transponder
JP2003298002A (ja) * 2002-04-02 2003-10-17 Mitsubishi Electric Corp 半導体モジュール
JP2003298003A (ja) * 2002-04-03 2003-10-17 Mitsubishi Electric Corp 半導体モジュール
JP3828473B2 (ja) * 2002-09-30 2006-10-04 株式会社東芝 積層型半導体装置及びその製造方法
US7779782B2 (en) * 2004-08-09 2010-08-24 Lam Research Systems and methods affecting profiles of solutions dispensed across microelectronic topographies during electroless plating processes

Family Cites Families (4)

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Publication number Priority date Publication date Assignee Title
GB1487945A (en) * 1974-11-20 1977-10-05 Ibm Semiconductor integrated circuit devices
JPS5915183B2 (ja) * 1976-08-16 1984-04-07 株式会社日立製作所 マトリツクス配線基板
FR2382101A1 (fr) * 1977-02-28 1978-09-22 Labo Electronique Physique Dispositif a semi-conducteur, comportant des pattes metalliques isolees
US4246595A (en) * 1977-03-08 1981-01-20 Matsushita Electric Industrial Co., Ltd. Electronics circuit device and method of making the same

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01500944A (ja) * 1986-09-26 1989-03-30 ゼネラル・エレクトリック・カンパニイ 多重チップ集積回路パッケージ、集積回路チップのパッケージ及び集積回路チップをパッケージする方法
JP2018531504A (ja) * 2015-09-02 2018-10-25 オキュラス ブイアール，エルエルシー 半導体デバイスの組立
US10878733B2 (en) 2015-09-02 2020-12-29 Facebook Technologies, Llc Assembly of semiconductor devices using multiple LED placement cycles
US10916192B2 (en) 2016-04-26 2021-02-09 Facebook Technologies, Llc Display with redundant light emitting devices
US11727869B2 (en) 2016-04-26 2023-08-15 Meta Platforms Technologies, Llc Display with redundant light emitting devices

Also Published As

Publication number Publication date
EP0178227A2 (en) 1986-04-16
DE3571535D1 (en) 1989-08-17
US4721995A (en) 1988-01-26
EP0178227B1 (en) 1989-07-12
JPH0577184B2 (https=) 1993-10-26
EP0178227A3 (en) 1987-08-26

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