CN101145548A - 通用封装基板及其应用机构 - Google Patents
通用封装基板及其应用机构 Download PDFInfo
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49112—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting a common bonding area on the semiconductor or solid-state body to different bonding areas outside the body, e.g. diverging wires
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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Abstract
一种用来承载芯片的通用封装基板,此通用封装基板包括:形成在封装基板一侧的复数个焊指部,其中芯片的焊垫通过打线与焊指部其中之一电性连结,且焊指部中至少二个位于打线的延伸方向上。
Description
技术领域
本发明涉及一种芯片封装技术,特别是一种通用的封装基板。
背景技术
半导体封装制程在基板的芯片载体(Chip Carrier)表面通过芯片键合(DieBond)与打线(Wire Bond)等制程完成芯片与基板的电性连结,再通过胶体封装(Encapsulation),甚至切刻作业,以形成半导体封装组件。
以球栅阵列封装(Ball Grid Array;BGA)基板为例,请参照图1,图1为根据现有技术所绘示的封装基板结构俯视图。封装基板100的铜质导线裸露在基板100阻焊层(Solder Mask)的焊指部(Bonding Finger),例如焊指部104a,可使芯片102通过打线(Bonding Wire)106与封装基板100的导线有效电性连接,再透过导线另一端的焊球(图未示)与外部电子组件形成电性连结。
现有的封装基板100通常会配合特定芯片102的结构加以设计,例如每一个焊指部(焊指部104a)都对应芯片102的一个焊垫(Bonding Pad)开窗(焊垫开窗101)。虽然这种设计具有芯片与封装基板的匹配性佳的优点。
然而,受到产品生命周期短,以及少量多样的设计需求,现有的配合每一种芯片的电路布局来设计专用封装基板的方式,制造者不仅需要负担额外设计与模具成本,又由于产品少量多样的要求,也使得制程交期较难掌握。
发明内容
因此需要提供一种通用封装基板,可适用多种芯片设计,以解决高制造成本与交期难以掌握的问题。
本发明的目的在提供一种用于乘载芯片的通用封装基板,这种通用封装基板包括:形成在封装基板一侧的复数个焊指部,其中芯片的第一焊垫通过第一打线与上述焊指部其中之一电性连结,并且至少有两个焊指部位于打线的延伸方向上。
本发明的另一目的是在提供一种封装结构,此封装结构包括芯片、通用封装基板、复个焊指部以及打线。其中通用基板用于承载芯片。焊指部形成在通用封装基板的一侧以定义出焊指部,其中芯片的焊垫通过打线与焊指部的其中之一电性连结,并且至少两个焊指部位于打线的延伸方向上。
根据以上所述的实施例,本发明采用通用封装基板来取代现有配合芯片结构所设计的专用封装基板,可以解决现有技术制造成本太高以及制程交期难以控制的问题。
本发明之目的特征及优点将以实施例结合附图进行详细说明。
附图说明
图1为现有技术封装基板结构的俯视图;
图2A为本发明的较佳实施例的球栅阵列封装结构的立体示意图;
图2B为本发明的较佳实施例的球栅阵列封装结构的俯视图;
图3为本发明另一较佳实施例的球栅阵列封装结构的立体示意图。
具体实施方式
本发明的目的就是在提供一种适用于多种芯片设计的通用封装基板,以解决制造成本偏高与交期难以控制的问题。
为了使能使本发明的特点和技术优势能有更清楚的呈现,以下举一球栅阵列封装结构作为较佳实施例来加以详细说明。
请参照图2A及图2B,图2A为根据本发明的较佳实施例所绘示的球栅阵列封装结构的立体示意图。图2B为根据本发明的较佳实施例所绘示的球栅阵列封装结构的俯视图。这种球栅阵列封装结构20包括一芯片202以及用来承载芯片202的通用封装基板200。其中,通用封装基板200包括:置晶区210以及复数条导线(图未示)。
置晶区210位于芯片202下方,用于承载芯片202的置晶区210。在本发明的实施例中,置晶区210可以是一个非实体的区域。例如在本实施例中,置晶区210指位于芯片202正下方的区域。
导线是形成在通用封装基板200内的复数条导线。每一条导线的一端由通用封装基板200阻焊层暴露在通用封装基板200的一侧,以定义出焊指部,例如焊指部204a、204b、204d和204e。在本发明的一些实施例中,如焊指部204a、204b、204d和204e为长方形。
其中每一个焊指部邻接置晶区210的一个侧边210a,并且与侧边210a相距有一段距离。其中每一个焊指部彼此平行排列,并且与侧边210a成一夹角,这个夹角实质介于15至165度之间。在本发明的一些实施例中,其中每一个焊指部例如焊指部204a及204b彼此平行排列,且与侧边210a的夹角为0度。
另外,在本发明的较佳实施例中,通用封装基板200可以进一步包括有电源环(Power ring)以及接地环(Ground ring),其中电源环212与接地环214分别邻接围绕置晶区210外围,并介于置晶区210和平行排列的焊指部之间,并且电源垫212与接地垫214分别与每一个焊指部座以及置晶区210的侧边210a相距有一段距离。然而,在本发明的另一较佳实施例中,经过适当的设计,电源环212以及接地环214可分别采用不同的焊指部来替代,请参照图3,图3为根据本发明的另一较佳实施例所绘示的球栅阵列封装结构的立体示意图。其中通用封装基板300采用焊指部204d来作为电源垫以取代电源环,采用焊指部204e来作为接地垫以取代接地环。
芯片202的第一焊垫201通过第一打线206a与焊指部中的其中之一例如焊指部204a电性连结,并且至少有两个焊指部,例如焊指部204a及204b,位于第一打线206a的延伸方向(箭头所示)208a上。芯片202的第二焊垫203通过第二打线206b与焊指部其中之一例如焊指部204b电性连结,并且至少两个焊指部,例如焊指部204b及204c位于第二打线206b的延伸方向(箭头所示)208b上。
在本发明的一些实施例中,并非每一个焊指部都通过一条打线与一个焊垫电性连结,其中打线、焊指部以及焊垫之间的电性连结是根据芯片202电路的布局加以设计。例如,第一打线206a与第二打线206b可能电性连结在不同的焊指部上,也可能同时电性连结在相同的焊指部上。
在本发明的一些实施例中,一个焊垫可能通过复数条打线分别与复数个焊指部电性连结。例如在本实施例中,第一焊垫201可通过第一打线206a及第三打线206c分别与焊指部204a及204d电性连结。
另外,为了配合各种不同芯片的线路设计,在本发明的一些实施例中,任意两个焊指部例如焊指部204d与204e之间可通过一条第四打线206d电性连结。但值得注意的是,每一条打线彼此之间相距有一段距离,并未相互接触。
根据以上所述的实施例,本发明的特点在于采用通用封装基板来取代现有配合芯片结构所设计的专用基板。其中通用封装基板至少具有两个焊指部,分别位于由芯片的焊垫所延伸出来的打线延伸方向上。此外,通用封装基板可配合不同芯片的线路布局进行打线处理,不需要为特定芯片量身定作特定的基板,可大幅减少产品设计与开发的模具成本,并且有利于制程管控与产品交期的掌握。
因此本发明确实可以通过提供一种适用于多种不同芯片的电路布局的通用封装基板来解决现有技术开发与制造成本太高,且制程交期难以控制的问题,以符合产品生命周期短,以及少量多样的设计需求的产业趋势。
以上所述仅为本发明其中的较佳实施例而已,并非用来限定本发明的实施范围;即凡依本发明权利要求所作的均等变化与修饰,皆为本发明专利范围所涵盖。
Claims (10)
1.一种通用封装基板,用于承载一芯片,其特征在于该通用封装基板包括:
复数个焊指部(Bonding Finger),形成在该基板一侧,该芯片的一第一焊垫(Bonding Pad)通过一第一打线(Bonding Wire)与该些焊指部其中之一电性连结,且该些焊指部其中至少二个位于该打线的延伸方向上。
2.如权利要求1所述的通用封装基板,其特征在于,进一步包括一第二打线,该些焊指部其中至少二个位于该第二打线的延伸方向上。
3.如权利要求2所述的通用封装基板,其特征在于,该第二打线用来使该芯片的一第二焊垫与该些焊指部其中之一电性连结。
4.如权利要求3所述的通用封装基板,其特征在于,该第一打线与该第二打线电性连结在相同的焊指部上。
5.如权利要求3所述的通用封装基板,其特征在于,该第一打线与该第二打线电性连结在不同的焊指部上。
6.如权利要求3所述的通用封装基板,其特征在于,至少包括一第三打线使该第二焊垫与该些焊指部其中之一电性连结。
7.如权利要求6所述的通用封装基板,其特征在于,该些焊指部的二者间可通过一第四打线电性连结。
8.如权利要求1所述的通用封装基板,其特征在于,其中每一该些焊指部系彼此平行排列且与该侧边成一夹角,该夹角系实质介于15至165度之间,该夹角亦可为0度。
9.如权利要求1所述的通用封装基板,其特征在于,进一步包括一电源环(Power ring)以及接地环(Ground ring),分别邻接该芯片,并分别与每一该些焊指部及该芯片相距有一距离。
10.一种封装结构,其特征在于包括:
一芯片;
一通用封装基板,用于乘载该芯片;
复数个焊指部,形成在该基板一侧;以及
一第一打线,用于电性连结该芯片的一第一焊垫与该些焊指部其中之一,且该些焊指部其中至少二个位于该第一打线的延伸方向上。
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102074510A (zh) * | 2010-11-11 | 2011-05-25 | 友达光电股份有限公司 | 接触垫阵列 |
CN102446881A (zh) * | 2011-12-12 | 2012-05-09 | 清华大学 | 一种通用封装基板及其封装方法 |
CN102522339A (zh) * | 2011-12-12 | 2012-06-27 | 清华大学 | 一种设计通用封装基板的方法 |
-
2006
- 2006-09-12 CN CNA2006101275416A patent/CN101145548A/zh active Pending
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102074510A (zh) * | 2010-11-11 | 2011-05-25 | 友达光电股份有限公司 | 接触垫阵列 |
CN102446881A (zh) * | 2011-12-12 | 2012-05-09 | 清华大学 | 一种通用封装基板及其封装方法 |
CN102522339A (zh) * | 2011-12-12 | 2012-06-27 | 清华大学 | 一种设计通用封装基板的方法 |
WO2013086755A1 (zh) * | 2011-12-12 | 2013-06-20 | 清华大学 | 一种设计通用封装基板的方法 |
CN102446881B (zh) * | 2011-12-12 | 2014-02-26 | 清华大学 | 一种通用封装基板及其封装方法 |
CN102522339B (zh) * | 2011-12-12 | 2014-10-22 | 清华大学 | 一种设计通用封装基板的方法 |
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