WO2013086755A1 - 一种设计通用封装基板的方法 - Google Patents

一种设计通用封装基板的方法 Download PDF

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Publication number
WO2013086755A1
WO2013086755A1 PCT/CN2011/084496 CN2011084496W WO2013086755A1 WO 2013086755 A1 WO2013086755 A1 WO 2013086755A1 CN 2011084496 W CN2011084496 W CN 2011084496W WO 2013086755 A1 WO2013086755 A1 WO 2013086755A1
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chip
type
pads
power
package substrate
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PCT/CN2011/084496
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English (en)
French (fr)
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蔡坚
浦园园
王谦
郭函
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清华大学
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Publication of WO2013086755A1 publication Critical patent/WO2013086755A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/485—Adaptation of interconnections, e.g. engineering charges, repair techniques
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48235—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0005—Apparatus or processes for manufacturing printed circuits for designing circuits by computer

Definitions

  • the present invention relates to the field of semiconductor packaging, and more particularly to a method of designing a general package substrate. Background technique
  • BGA Ball Grid Array
  • I/O ports large pitch and high reliability.
  • the use of short pins and good coplanarity has led to rapid growth in applications in light, small, and high-performance devices, and has evolved into a mature high-density packaging technology.
  • 1 shows a schematic diagram of a conventional BGA package in the form of a wire bonding, in which reference numeral 20 denotes a packaged chip, reference numeral 104 denotes a wire, reference numeral 105 denotes a through hole, reference numeral 103 denotes a substrate, and reference numeral 106 denotes a ball.
  • the current BGA package is in the phase of chip design and package design, which makes the substrate design different from chip to chip, that is, the independently developed chip needs to be equipped with a separately designed package substrate, so whether it is a sample or a product
  • the cost of pre-package design can be allocated to the cost of the product, but the impact is small, but for small-volume chip packages, because of the small size and high cost, if a new package is needed
  • the design will further increase the cost. Therefore, there is an urgent need to design a general-purpose package substrate to meet the requirements of small-volume chip packages. Summary of the invention
  • the present invention is directed to the disadvantages of high packaging cost and long packaging period when packaging small-volume chips in the prior art, and provides a method for designing a general-purpose package substrate that can overcome the above disadvantages.
  • the present invention provides a method of designing a general package substrate, the method comprising:
  • the size of the general purpose package substrate for this type of chip is determined based on the maximum chip size of each type of chip, the determined number and distribution of bond pads, and the determined number and distribution of power supply pads.
  • the method of designing a general-purpose package substrate according to the present invention first divides the chip type according to parameters such as power supply requirements, operating frequency, chip size, and pin count, and then determines a general-purpose package suitable for each type of chip for the divided chip type.
  • Substrate parameters including substrate size, substrate material, substrate bonding pad, substrate power pad, etc.
  • a chip can be used to package the chips belonging to the divided chip types, thereby saving packaging costs and reducing packaging cycles.
  • the method of packaging a small-volume chip according to the present invention also considers the performance requirements of the chip, such as power supply requirements, operating frequency, power pad distribution, and bond pad distribution, it does not cause chip performance degradation.
  • Figure 1 shows a schematic cross-sectional view of a BGA package in the form of a wire
  • FIG. 2 is a flow chart of a method of packaging a small-volume chip according to the present invention
  • 3 is a top plan view of a general purpose package substrate in accordance with the present invention.
  • 4 is a bottom view of a general purpose package substrate in accordance with the present invention.
  • a method for designing a general-purpose package substrate according to the present invention includes:
  • the number of bonding pads on the general-purpose package substrate can be determined to be greater than or equal to the number of pins of the chip having the largest number of pins in the chip, so that the number of pins can be Each chip in the class chip having a different number of pins is packaged.
  • the number of power pads on the general-purpose package substrate may be determined to be greater than or equal to the number of power pins of the chip having the largest number of power pins in the chip, so that A single set of power chips and a chip with multiple sets of power supplies can be packaged.
  • the power pad when determining the distribution of the power pad, can be formed into a power ring, and the power ring is located between the edge of the chip and the bonding pad on the universal package substrate and the power ring is Intermittently, as shown in the top view of the general package substrate in FIG.
  • reference numeral 201 denotes a general-purpose package substrate
  • reference numeral 203 denotes a bonding pad
  • reference numeral 204 denotes a power supply ring
  • reference numeral 202 denotes a die bonding region.
  • the power pad on the general package substrate can also be located only on one side of the chip.
  • the wiring design on the general package substrate is not shown in FIG. 2, and When packaging, when the number of pads of the chip is smaller than the number of pads on the general package substrate, the excess pads on the general package substrate may be vacant or grounded.
  • the number and distribution of the power pad and the bonding pad enumerated in the present invention are only schematic, and do not constitute a limitation of the present invention.
  • the general package substrate The number and distribution of power pads and bond pads on the top are also different.
  • the size of the power pad and the bonding pad are wider and longer than those of the conventional power pad and bonding pad used in the prior art, so as to be applicable to each chip package in one type of chip. .
  • the determined material and line width of the substrate should also be the material and line width suitable for the strobe chip so as not to affect the overall performance of the chip.
  • This step is mainly to consider that the distance between the chip and the pad on the substrate should not be too short or too long, because the machine that is too short can not be completed, and the gold wire used for bonding cannot be supported if it is too long.
  • the distance between the die pad and the bond pads on the substrate is in the range of 400 ⁇ to 3000 ⁇ .
  • the universal package substrate is designed. This needs to be considered when designing chips in the future.
  • the general package substrate size, the power supply pad on the general package substrate, and the bonding pad make parameters such as chip size, pin count, and pad distribution as large as possible to meet the parameter requirements of the general package substrate suitable for such chips. This eliminates the need to redesign the substrate, saving cost and reducing package design time.
  • a method of designing a general-purpose package substrate according to the present invention further includes: designing a bottom pad on a side of the general-purpose package substrate on which the chip is not pasted into a full array form, and There is a one-to-one or many-to-one relationship between the sum of the number of bonding pads and the power pad and the bottom pad.
  • the bottom pad is used to connect the universal package substrate and the motherboard.
  • FIG. 3 is a surface array distribution.
  • the peripheral bonding pads of the bonding pads are connected to the bottom pad of the central region in the bottom array of the full array form, and the bonding pads are located at the center
  • the bonding pad of the region is connected to the bottom pad of the peripheral region in the bottom pad of the full array form, and the general package substrate according to the present invention is thus wired so that the chip to be packaged is large in size, the chip When the number of pads is large, a full array of BGA packages can be formed, and when the chip to be packaged is small in size and the number of chip pads is small, the bottom pad located in the center area can be avoided, thereby forming a non-full array BGA. Package.
  • a method of designing a general package substrate according to the present invention further comprises: determining a laminated structure of a substrate for the type of chip according to a wiring density and a distribution of power pads. Further, the method further includes: determining a thickness of the substrate for the type of chip based on the stacked structure. Thereby, the design of the substrate is further optimized.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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Abstract

一种设计通用封装基板的方法，该方法包括：根据供电要求、工作频率、芯片尺寸和管脚数来划分芯片类型（S11）；根据每种类型芯片的管脚数确定针对该种类型芯片的通用封装基板上的键合焊盘的数量和分布，其中所述键合焊盘为基板上除了电源焊盘之外的焊盘（S12）；根据每种类型芯片的供电要求确定针对该种类型芯片的通用封装基板上的电源焊盘的数量和分布（S13）；根据每种类型芯片的工作频率确定针对该种类型芯片的通用封装基板的材料和线宽（S14）；以及根据每种类型芯片的最大芯片尺寸、所确定的键合焊盘的数量和分布以及所确定的电源焊盘的数量和分布来确定针对该种类型芯片的通用封装基板的尺寸（S15）。

Description

一种设计通用封装基板的方法 技术领域
本发明涉及半导体封装领域， 尤其涉及一种设计通用封装基板的方法。 背景技术
电子元器件的飞速发展对半导体封装技术提出了越来越高的要求。 目 前， 焊球阵列 （Ball Grid Array, BGA) 封装技术是 20世纪 90年代以后发 展起来的一种先进的高性能面阵列封装技术， 其因 I/O端口数多、 节距大、 可靠性高、 引脚很短和共面性好等优点而在轻、 小、 高性能器件中应用迅 速增长， 并发展成为一门成熟的高密度封装技术。 图 1 示出了现有的打线 形式的 BGA封装示意图， 其中， 标号 20表示被封装的芯片， 标号 104表 示打线， 标号 105表示通孔， 标号 103表示基板， 标号 106表示悍球。
但是， 目前的 BGA封装处于芯片设计和封装设计相脱离的阶段， 这使 得基板设计会因芯片的不同而不同， 即独立开发的芯片需要配以单独设计 的封装基板， 因此， 无论是样片还是产品都需要前期封装的研发， 这不仅 花费了大量的费用而且还会因基板的设计和制备而延长封装周期。 对于大 批量芯片封装而言， 前期封装设计费用可以分摊到产品成本中， 影响不大， 但对于小批量芯片封装而言， 由于其产品规模不大并且成本较高， 如果还 要进行新的封装设计的话会更进一步增加成本。 因此， 迫切需要设计一种 通用封装基板来满足小批量芯片封装的要求。 发明内容
本发明针对现有技术中在封装小批量芯片时封装成本高、 封装周期长 的缺点， 提供一种能够克服上述缺点的设计通用封装基板的方法。 本发明提供一种设计通用封装基板的方法， 该方法包括：
根据供电要求、 工作频率、 芯片尺寸和管脚数来划分芯片类型； 根据每种类型芯片的管脚数确定针对该种类型芯片的通用封装基板上 的键合焊盘的数量和分布， 其中所述键合悍盘为基板上除了电源焊盘之外 的焊盘；
根据每种类型芯片的供电要求确定针对该种类型芯片的通用封装基板 上的电源焊盘的数量和分布；
根据每种类型芯片的工作频率确定针对该种类型芯片的通用封装基板 的材料和线宽； 以及
根据每种类型芯片的最大芯片尺寸、 所确定的键合焊盘的数量和分布 以及所确定的电源焊盘的数量和分布来确定针对该种类型芯片的通用封装 基板的尺寸。
由于根据本发明的设计通用封装基板的方法首先根据供电要求、 工作 频率、 芯片尺寸和管脚数等参数来划分芯片类型， 然后针对所划分的芯片 类型确定适用于每种类型的芯片的通用封装基板参数 （包括基板尺寸、 基 板材料、 基板键合焊盘、 基板电源焊盘等参数）， 从而得到一种适用于封装 该种类型芯片的通用封装基板， 这样在封装属于所划分芯片类型的小批量 芯片时就不必重新设计基板， 而是能够用一款基板来封装属于所划分芯片 类型的芯片， 从而节省了封装成本并减少了封装周期。 另外， 由于根据本 发明的封装小批量芯片的方法还考虑了芯片的供电要求、 工作频率、 电源 焊盘分布和键合焊盘分布等性能要求， 所以不会导致芯片性能折损。 附图说明
图 1示出了一种打线形式的 BGA封装截面示意图;
图 2是根据本发明的封装小批量芯片的方法的流程
图 3是根据本发明的通用封装基板的俯视图； 图 4是根据本发明的通用封装基板的底视图。 具体实施方式
下面结合附图来详细描述根据本发明的设计通用封装基板的方法。 如图 1所示， 根据本发明的设计通用封装基板的方法包括：
511、 根据供电要求、 工作频率、 芯片尺寸和管脚数来划分芯片类型。 通常在供电要求、 工作频率、 芯片尺寸和管脚数等方面比较类似的各 种芯片， 其封装所用的基板也比较类似， 从而使得能够针对一种类型的芯 片仅设计一款能够对这种类型的芯片进行封装的通用封装基板， 避免了芯 片设计完成之后再根据所设计的芯片来设计封装所用基板的需求。
512、根据每种类型芯片的管脚数确定针对该种类型芯片的通用封装基 板上的键合焊盘的数量和分布， 其中所述键合焊盘为通用封装基板上除了 电源悍盘之外的焊盘。
在根据本发明的一个优选实施方式中， 可以将通用封装基板上的键合 焊盘的数量确定为大于或等于该类芯片中具有最大数量管脚数的芯片的管 脚数， 从而能够对该类芯片中具有不同管脚数的各个芯片进行封装。 另外， 在对键合焊盘的分布进行确定时， 也需要考虑一类芯片中各个芯片的键合 焊盘的分布， 以便能够对该类芯片中具有不同键合焊盘分布形式的各个芯 片进行封装。
513、根据每种类型芯片的供电要求确定针对该种类型芯片的通用封装 基板上的电源焊盘的数量和分布。
在根据本发明的一个优选实施方式中， 可以将通用封装基板上的电源 焊盘的数量确定为大于或等于该类芯片中具有最大数量的电源管脚的芯片 的电源管脚数， 以便对具有单组电源的芯片和具有多组电源的芯片都能够 进行封装。 另外， 在确定电源焊盘的分布时， 可以使电源焊盘形成电源环， 并且该电源环位于芯片边缘与通用封装基板上的键合悍盘之间且电源环呈 断续状， 如图 2 中的通用封装基板俯视图所示意性示出的那样， 其中标号 201表示通用封装基板， 标号 203表示键合焊盘， 标号 204表示电源环， 标 号 202表示芯片粘结区。 当然， 根据一类芯片的电源焊盘分布形式， 通用 封装基板上的电源焊盘也可以只位于芯片的一侧边缘。 另外， 应当理解的 是， 由于即使被划分为同一类的芯片， 其管脚数、 焊盘分布等也会有所不 同， 所以图 2 中并未示出通用封装基板上的布线设计， 而且， 在封装时， 当芯片的焊盘数小于通用封装基板上的焊盘数量时， 通用封装基板上多余 的焊盘可以空置或接地。 本领域技术人员还应当理解， 本发明中所列举的 电源焊盘和键合悍盘的数量和分布仅是示意性的， 其并不构成对本发明的 限制， 根据芯片分类的不同， 通用封装基板上的电源焊盘和键合焊盘的数 量和分布也是不同的。 而且优选地， 电源焊盘和键合焊盘的尺寸要比现有 技术中所采用的一般电源焊盘和键合焊盘的尺寸宽和长， 以便能够适用于 一类芯片中的各个芯片封装。
514、根据每种类型芯片的工作频率确定针对该种类型芯片的基板的材 料和线宽。
例如， 当该种类型的芯片的工作频率为高频时， 所确定的基板的材料 和线宽也应当是适用于髙频芯片的材料和线宽， 以便不影响芯片的整体性 能。
515、 根据每种类型芯片的最大芯片尺寸、 所确定的键合焊盘的数量和 分布以及所确定的电源焊盘的数量和分布来确定针对该种类型芯片的通用 封装基板的尺寸。
该步骤主要是考虑到芯片与基板上的焊盘之间的距离不能过短或过 长， 因为过短则键合的机器无法完成， 过长则用于键合的金线无法支持。 通常， 芯片焊盘与基板上的键合焊盘之间的距离在 400μηι至 3000μηι的范 围内。
至此， 通用封装基板就设计完成了。 这样在今后设计芯片时需要考虑 通用封装基板尺寸、 通用封装基板上的电源悍盘和键合焊盘等参数， 使得 芯片的尺寸、 管脚数、 焊盘分布等参数尽量满足适用于该类芯片的通用封 装基板的参数要求， 从而也就不需要重新设计基板， 从而节省了成本、 降 低了封装设计时间。
在根据本发明的一个优选实施方式中， 根据本发明的设计通用封装基 板的方法还包括： 将位于所述通用封装基板的不粘贴芯片的一侧上的底部 焊盘设计为全阵列形式， 并且所述键合焊盘和所述电源焊盘的数量总和与 所述底部焊盘之间是一对一或多对一的关系。 其中， 底部焊盘用于连接所 述通用封装基板和母板， 其示意图如图 3所示， 其为面阵列分布。 而且， 优选地， 所述键合焊盘中的位于外围的键合焊盘连接到全阵列形式的底部 焊盘中的位于中心区域的底部焊盘， 而所述键合焊盘中的位于中心区域的 键合悍盘连接到全阵列形式的底部焊盘中的位于外围区域的底部焊盘， 通 过对根据本发明的通用封装基板进行如此布线， 使得当要被封装的芯片尺 寸较大、 芯片焊盘数量较多时可以形成一个全阵列的 BGA封装， 而当要被 封装的芯片尺寸较小、 芯片焊盘数量较少时可以避免使用位于中心区域的 底部焊盘， 从而形成非全阵列的 BGA封装。
在根据本发明的一个优选实施方式中， 根据本发明的设计通用封装基 板的方法还包括： 根据布线密度和电源焊盘的分布， 确定针对该种类型芯 片的基板的叠层结构。 进一步地， 该方法还包括： 根据所述叠层结构确定 针对该种类型芯片的基板的厚度。 从而， 进一步优化了基板的设计。
以上仅结合本发明的优选实施方式对本发明进行了详细描述， 但是应 当理解， 在不背离本发明精神和范围的情况下， 可以对本发明进行各种变 形和修改。

Claims

权利要求
1、 一种设计通用封装基板的方法， 该方法包括：
根据供电要求、 工作频率、 芯片尺寸和管脚数来划分芯片类型： 根据每种类型芯片的管脚数确定针对该种类型芯片的通用封装基板上 的键合焊盘的数量和分布， 其中所述键合焊盘为基板上除了电源焊盘之外 的焊盘；
根据每种类型芯片的供电要求确定针对该种类型芯片的通用封装基板 上的电源焊盘的数量和分布；
根据每种类型芯片的工作频率确定针对该种类型芯片的通用封装基板 的材料和线宽； 以及
根据每种类型芯片的最大芯片尺寸、 所确定的键合悍盘的数量和分布 以及所确定的电源焊盘的数量和分布来确定针对该种类型芯片的通用封装 基板的尺寸。
2、 根据权利要求 1所述的方法， 其中， 根据每种类型芯片的管脚数确 定针对该种类型芯片的通用封装基板上的键合焊盘的数量包括： 将通用封 装基板上的键合悍盘的数量确定为大于或等于该类芯片中具有最大数量管 脚数的芯片的管脚数。
3、 根据权利要求 1所述的方法， 其中， 根据每种类型芯片的供电要求 确定针对该种类型芯片的通用封装基板上的电源焊盘的数量包括： 将通用 封装基板上的电源焊盘的数量确定为大于或等于该类芯片中具有最大数量 的电源管脚的芯片的电源管脚数。
4、 根据权利要求 1所述的方法， 其中， 所述电源焊盘形成电源环， 并 且所述电源环位于芯片边缘与所述键合焊盘之间且所述电源环呈断续状。
5、 根据权利要求 1所述的方法， 其中， 该方法还包括： 将位于所述通 用封装基板的不粘贴芯片的一侧上的底部焊盘设计为全阵列形式， 并且所 述键合焊盘和所述电源焊盘的数量总和与所述底部焊盘之间是一对一或多 对一的关系。
6、 根据权利要求 5所述的方法， 其中， 所述键合焊盘中的位于外围的 键合焊盘连接到全阵列形式的底部焊盘中的位于中心区域的底部悍盘， 而 所述键合焊盘中的位于中心区域的键合焊盘连接到全阵列形式的底部焊盘 中的位于外围区域的底部焊盘。
7、 根据权利要求 1所述的方法， 其中， 该方法还包括： 根据布线密度 和电源焊盘的分布， 确定针对该种类型芯片的通用封装基板的叠层结构。
8、 根据权利要求 7所述的方法， 其中， 该方法还包括： 根据所述叠层 结构确定针对该种类型芯片的通用封装基板的厚度。
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