JPS61105851A - ワイヤボンデイング方法 - Google Patents

ワイヤボンデイング方法

Info

Publication number
JPS61105851A
JPS61105851A JP59228507A JP22850784A JPS61105851A JP S61105851 A JPS61105851 A JP S61105851A JP 59228507 A JP59228507 A JP 59228507A JP 22850784 A JP22850784 A JP 22850784A JP S61105851 A JPS61105851 A JP S61105851A
Authority
JP
Japan
Prior art keywords
bonding
wire
pads
wire bonding
wires
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59228507A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0365894B2 (enExample
Inventor
Kohei Suzuki
公平 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP59228507A priority Critical patent/JPS61105851A/ja
Publication of JPS61105851A publication Critical patent/JPS61105851A/ja
Publication of JPH0365894B2 publication Critical patent/JPH0365894B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
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    • H01L2224/061—Disposition
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    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48471—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
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    • H01L2924/0001—Technical content checked by a classifier
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    • H01L2924/01015—Phosphorus [P]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
JP59228507A 1984-10-30 1984-10-30 ワイヤボンデイング方法 Granted JPS61105851A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59228507A JPS61105851A (ja) 1984-10-30 1984-10-30 ワイヤボンデイング方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59228507A JPS61105851A (ja) 1984-10-30 1984-10-30 ワイヤボンデイング方法

Publications (2)

Publication Number Publication Date
JPS61105851A true JPS61105851A (ja) 1986-05-23
JPH0365894B2 JPH0365894B2 (enExample) 1991-10-15

Family

ID=16877521

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59228507A Granted JPS61105851A (ja) 1984-10-30 1984-10-30 ワイヤボンデイング方法

Country Status (1)

Country Link
JP (1) JPS61105851A (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS647530A (en) * 1987-06-29 1989-01-11 Nec Corp Manufacture of semiconductor device
US9281289B2 (en) 2013-07-30 2016-03-08 Renesas Electronics Corporation Semiconductor device and method of manufacturing the same

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5694119B2 (ja) * 2010-11-25 2015-04-01 三菱電機株式会社 炭化珪素半導体装置

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS647530A (en) * 1987-06-29 1989-01-11 Nec Corp Manufacture of semiconductor device
US9281289B2 (en) 2013-07-30 2016-03-08 Renesas Electronics Corporation Semiconductor device and method of manufacturing the same
TWI631680B (zh) * 2013-07-30 2018-08-01 Renesas Electronics Corporation 半導體裝置
US10170402B2 (en) 2013-07-30 2019-01-01 Renesas Electronics Corporation Semiconductor device

Also Published As

Publication number Publication date
JPH0365894B2 (enExample) 1991-10-15

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