JPS61100176U - - Google Patents

Info

Publication number
JPS61100176U
JPS61100176U JP18629584U JP18629584U JPS61100176U JP S61100176 U JPS61100176 U JP S61100176U JP 18629584 U JP18629584 U JP 18629584U JP 18629584 U JP18629584 U JP 18629584U JP S61100176 U JPS61100176 U JP S61100176U
Authority
JP
Japan
Prior art keywords
chip component
component mounting
printed wiring
view
land
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18629584U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP18629584U priority Critical patent/JPS61100176U/ja
Publication of JPS61100176U publication Critical patent/JPS61100176U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図aは本考案に係るプリント配線基板の一
実施例の要部平面図、第1図bは第1図aの断面
図、第2図は従来のプリント配線基板およびその
実装状態を示す要部断面図、第3図aはチツプ部
品を搭載するためのランドとクリーム半田の関係
を示す側面図、第3図bは第3図aにチツプ部品
を搭載した側面図、第4図aはチツプ部品ランド
にスルーホールが近接して配置されたときのチツ
プ部品が実装された状態の平面図、第4図bは第
3図aの断面図、第5図はチツプ部品ランドが近
接して配置されたときのチツプ部品が実装された
状態の平面図である。 1……プリント配線基板、4……スルーホール
メツキ部、11……チツプ部品を搭載するランド
、21……マーキング部材。
Figure 1a is a plan view of essential parts of an embodiment of the printed wiring board according to the present invention, Figure 1b is a sectional view of Figure 1a, and Figure 2 shows a conventional printed wiring board and its mounting state. 3a is a side view showing the relationship between the land and cream solder for mounting chip components; FIG. 3b is a side view of FIG. 3a with chip components mounted; FIG. 4a is a plan view of the chip component mounted when the through hole is placed close to the chip component land, FIG. 4b is a sectional view of FIG. 3a, and FIG. FIG. 3 is a plan view of a state in which chip components are mounted when arranged as shown in FIG. DESCRIPTION OF SYMBOLS 1... Printed wiring board, 4... Through-hole plating part, 11... Land on which chip parts are mounted, 21... Marking member.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 近接して配接されたチツプ部品搭載用ランドの
間と、チツプ部品搭載用ランドとスルーホールメ
ツキ部の間の少なくとも一方に、所要の厚さのマ
ーキング部材を設けたことを特徴とするプリント
配線基板。
A printed wiring characterized in that a marking member of a required thickness is provided between at least one of the adjacent chip component mounting lands and between the chip component mounting land and the through-hole plated portion. substrate.
JP18629584U 1984-12-07 1984-12-07 Pending JPS61100176U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18629584U JPS61100176U (en) 1984-12-07 1984-12-07

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18629584U JPS61100176U (en) 1984-12-07 1984-12-07

Publications (1)

Publication Number Publication Date
JPS61100176U true JPS61100176U (en) 1986-06-26

Family

ID=30743762

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18629584U Pending JPS61100176U (en) 1984-12-07 1984-12-07

Country Status (1)

Country Link
JP (1) JPS61100176U (en)

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