JPS63162568U - - Google Patents
Info
- Publication number
- JPS63162568U JPS63162568U JP5436487U JP5436487U JPS63162568U JP S63162568 U JPS63162568 U JP S63162568U JP 5436487 U JP5436487 U JP 5436487U JP 5436487 U JP5436487 U JP 5436487U JP S63162568 U JPS63162568 U JP S63162568U
- Authority
- JP
- Japan
- Prior art keywords
- solder resist
- resist layer
- groove
- land
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910000679 solder Inorganic materials 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims 2
- 230000000149 penetrating effect Effects 0.000 claims 1
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Description
第１図ａ，ｂは本考案の第１の実施例を示す平
面図およびＡ―Ａ′線断面図、第２図は第１図の
印刷配線板にチツプ部品を搭載したときの断面図
、第３図は本考案の第２の実施例を示す平面図、
第４図は本考案の第３の実施例を示す平面図、第
５図は従来の印刷配線板にチツプ部品を搭載した
ときの断面図である。
１……絶縁基板、２……ランド、３……はんだ
、４……ソルダレジスト層、５……チツプ部品、
６……端子、７……貫通孔、８……第１の溝、９
……第２の溝、１０……配線層。
1A and 1B are a plan view and a sectional view taken along the line A-A' of the first embodiment of the present invention, and FIG. 2 is a sectional view of the printed wiring board shown in FIG. FIG. 3 is a plan view showing a second embodiment of the present invention;
FIG. 4 is a plan view showing a third embodiment of the present invention, and FIG. 5 is a sectional view when chip components are mounted on a conventional printed wiring board. DESCRIPTION OF SYMBOLS 1... Insulating board, 2... Land, 3... Solder, 4... Solder resist layer, 5... Chip parts,
6...Terminal, 7...Through hole, 8...First groove, 9
...Second groove, 10...Wiring layer.
Claims (1)
、該ランドに接続する配線層と、前記ランドの外
周に一定の間隔をおき、かつ前記配線層とその近
傍を被覆して前記ランドとの間に一定幅の溝を形
成するソルダレジスタ層を有する印刷配線板にお
いて、前記第１の溝近傍の前記ソルダレジスト層
が被覆された領域に前記ソルダレジスト層と前記
絶縁基板を貫通して設けられた貫通孔と、該貫通
孔と前記第１の溝を連結するように前記ソルダレ
ジスト層に設けられた第２の溝を有することを特
徴とする印刷配線板。 A component mounting land provided on an insulating substrate, a wiring layer connected to the land, and a wiring layer that is spaced apart from the land by a certain distance around the outer periphery of the land, and which covers the wiring layer and its vicinity. In a printed wiring board having a solder resist layer forming a groove of a constant width, a solder resist layer is provided in a region covered with the solder resist layer near the first groove, penetrating through the solder resist layer and the insulating substrate. A printed wiring board comprising a through hole and a second groove provided in the solder resist layer so as to connect the through hole and the first groove.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5436487U JPS63162568U (en) | 1987-04-10 | 1987-04-10 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5436487U JPS63162568U (en) | 1987-04-10 | 1987-04-10 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63162568U true JPS63162568U (en) | 1988-10-24 |
Family
ID=30881290
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5436487U Pending JPS63162568U (en) | 1987-04-10 | 1987-04-10 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63162568U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0328775U (en) * | 1989-07-29 | 1991-03-22 |
-
1987
- 1987-04-10 JP JP5436487U patent/JPS63162568U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0328775U (en) * | 1989-07-29 | 1991-03-22 |