JPS63162567U - - Google Patents
Info
- Publication number
- JPS63162567U JPS63162567U JP5436387U JP5436387U JPS63162567U JP S63162567 U JPS63162567 U JP S63162567U JP 5436387 U JP5436387 U JP 5436387U JP 5436387 U JP5436387 U JP 5436387U JP S63162567 U JPS63162567 U JP S63162567U
- Authority
- JP
- Japan
- Prior art keywords
- land
- wiring board
- printed wiring
- wiring layer
- insulating substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910000679 solder Inorganic materials 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Description
第１図ａ，ｂは本考案の第１の実施例を示す平
面図およびＡ―Ａ′線断面図、第２図は第１図の
印刷配線板にチツプ部品を搭載したときの断面図
、第３図は本考案の第２の実施例を示す平面図、
第４図は本考案の第３の実施例を示す平面図、第
５図は本考案の第４の実施例を示す平面図、第６
図は本考案の第５の実施例を示す平面図、第７図
は本考案の第６の実施例を示す平面図、第８図は
従来の印刷配線板にチツプ部品を搭載したときの
断面図である。
１……絶縁基板、２……ランド、３……はんだ
、４……ソルダレジスタ層、５……チツプ部品、
６……端子、７……貫通孔、８……溝、９……配
線層。
1A and 1B are a plan view and a cross-sectional view taken along the line A-A' of the first embodiment of the present invention, and FIG. 2 is a cross-sectional view of the printed circuit board shown in FIG. FIG. 3 is a plan view showing a second embodiment of the present invention;
Fig. 4 is a plan view showing the third embodiment of the present invention, Fig. 5 is a plan view showing the fourth embodiment of the invention, and Fig. 6 is a plan view showing the fourth embodiment of the invention.
The figure is a plan view showing the fifth embodiment of the present invention, Fig. 7 is a plan view showing the sixth embodiment of the present invention, and Fig. 8 is a cross section of a conventional printed wiring board when chip components are mounted. It is a diagram. DESCRIPTION OF SYMBOLS 1... Insulating board, 2... Land, 3... Solder, 4... Solder resistor layer, 5... Chip component,
6...Terminal, 7...Through hole, 8...Groove, 9...Wiring layer.
Claims (1)
、該ランドに接続する配線層と、前記ランドの外
周に一定の間隔をおき、かつ前記配線層とその近
傍を被覆して前記ランドとの間に一定幅の溝を形
成するソルダレジスト層を有する印刷配線板にお
いて、前記絶縁基板に前記溝の一部に接続して設
けられた貫通孔を有することを特徴とする印刷配
線板。 A component mounting land provided on an insulating substrate, a wiring layer connected to the land, and a wiring layer that is spaced apart from the land at a certain distance around the outer periphery of the land, and that covers the wiring layer and its vicinity. 1. A printed wiring board having a solder resist layer forming grooves of a constant width in the printed wiring board, the printed wiring board having a through hole connected to a part of the groove in the insulating substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5436387U JPS63162567U (en) | 1987-04-10 | 1987-04-10 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5436387U JPS63162567U (en) | 1987-04-10 | 1987-04-10 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63162567U true JPS63162567U (en) | 1988-10-24 |
Family
ID=30881288
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5436387U Pending JPS63162567U (en) | 1987-04-10 | 1987-04-10 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63162567U (en) |
-
1987
- 1987-04-10 JP JP5436387U patent/JPS63162567U/ja active Pending