JPS6236570U - - Google Patents

Info

Publication number
JPS6236570U
JPS6236570U JP12828985U JP12828985U JPS6236570U JP S6236570 U JPS6236570 U JP S6236570U JP 12828985 U JP12828985 U JP 12828985U JP 12828985 U JP12828985 U JP 12828985U JP S6236570 U JPS6236570 U JP S6236570U
Authority
JP
Japan
Prior art keywords
wiring board
printed wiring
substrate
hole
state
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12828985U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP12828985U priority Critical patent/JPS6236570U/ja
Publication of JPS6236570U publication Critical patent/JPS6236570U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の一実施例を示す印刷配線板の
平面図、第2図はその配線板に形成されたスルー
ホールの断面図、第3図は前記印刷配線板に対す
る半田の付着状態を示す図、第4図は本考案の他
の一実施例を示す印刷配線板の断面図である。 1……基板、2a,2b……導電パターン、3
……スルーホール、4……導電層。
Fig. 1 is a plan view of a printed wiring board showing an embodiment of the present invention, Fig. 2 is a sectional view of through holes formed in the wiring board, and Fig. 3 shows the state of solder adhesion to the printed wiring board. The figure shown in FIG. 4 is a sectional view of a printed wiring board showing another embodiment of the present invention. 1...Substrate, 2a, 2b...Conductive pattern, 3
...Through hole, 4...Conductive layer.

Claims (1)

【実用新案登録請求の範囲】 基板表面に形成した導電パターンと導通する状
態でスルーホール内面に導電層が形成された印刷
配線板において、 前記スルーホール内の導電層のみが酸化され、
基板表面の導電パターンは酸化されない状態で形
成されていることを特徴とする印刷配線板。
[Claims for Utility Model Registration] In a printed wiring board in which a conductive layer is formed on the inner surface of a through hole in a state of being electrically connected to a conductive pattern formed on a surface of a substrate, only the conductive layer within the through hole is oxidized,
A printed wiring board characterized in that a conductive pattern on the surface of the substrate is formed in a state where it is not oxidized.
JP12828985U 1985-08-22 1985-08-22 Pending JPS6236570U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12828985U JPS6236570U (en) 1985-08-22 1985-08-22

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12828985U JPS6236570U (en) 1985-08-22 1985-08-22

Publications (1)

Publication Number Publication Date
JPS6236570U true JPS6236570U (en) 1987-03-04

Family

ID=31023826

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12828985U Pending JPS6236570U (en) 1985-08-22 1985-08-22

Country Status (1)

Country Link
JP (1) JPS6236570U (en)

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