JPS61131876U - - Google Patents

Info

Publication number
JPS61131876U
JPS61131876U JP1501185U JP1501185U JPS61131876U JP S61131876 U JPS61131876 U JP S61131876U JP 1501185 U JP1501185 U JP 1501185U JP 1501185 U JP1501185 U JP 1501185U JP S61131876 U JPS61131876 U JP S61131876U
Authority
JP
Japan
Prior art keywords
multilayer
wiring pattern
auxiliary
inner layer
multilayer substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1501185U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1501185U priority Critical patent/JPS61131876U/ja
Publication of JPS61131876U publication Critical patent/JPS61131876U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの考案の一実施例の多層プリント配
線基板の断面図、第2図は従来例の断面図である
。 1……多層基板、1a……表面、1b……内層
部分、2……外層配線パターン、3……内層配線
パターン、8……補助スルーホール、9……導電
部、10……迂回接続部分。
FIG. 1 is a sectional view of a multilayer printed wiring board according to an embodiment of this invention, and FIG. 2 is a sectional view of a conventional example. DESCRIPTION OF SYMBOLS 1... Multilayer board, 1a... Surface, 1b... Inner layer part, 2... Outer layer wiring pattern, 3... Inner layer wiring pattern, 8... Auxiliary through hole, 9... Conductive part, 10... Detour connection part .

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 多層配線パターンおよび内層配線パターンを形
成した多層基板と、この多層基板における前記内
層配線パターンを形成している内層部分から前記
多層配線パターンを形成している側の前記多層基
板の表面にかけて前記多層基板に形成した対の補
助スルーホールと、この対の補助スルーホールに
形成した導電部と、これらの導電部を前記多層基
板の表面で接続した迂回接続部分とを備えた多層
プリント配線基板。
a multilayer substrate on which a multilayer wiring pattern and an inner layer wiring pattern are formed; and a multilayer substrate from the inner layer portion of the multilayer substrate forming the inner layer wiring pattern to the surface of the multilayer substrate on the side where the multilayer wiring pattern is formed. A multilayer printed wiring board comprising: a pair of auxiliary through holes formed in the auxiliary through hole; a conductive part formed in the pair of auxiliary through holes; and a detour connection part in which these conductive parts are connected on the surface of the multilayer board.
JP1501185U 1985-02-05 1985-02-05 Pending JPS61131876U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1501185U JPS61131876U (en) 1985-02-05 1985-02-05

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1501185U JPS61131876U (en) 1985-02-05 1985-02-05

Publications (1)

Publication Number Publication Date
JPS61131876U true JPS61131876U (en) 1986-08-18

Family

ID=30500461

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1501185U Pending JPS61131876U (en) 1985-02-05 1985-02-05

Country Status (1)

Country Link
JP (1) JPS61131876U (en)

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